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74LVT16646ADGG

产品描述IC LVT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, Bus Driver/Transceiver
产品类别逻辑   
文件大小101KB,共21页
制造商NXP(恩智浦)
官网地址https://www.nxp.com
标准  
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74LVT16646ADGG概述

IC LVT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, Bus Driver/Transceiver

74LVT16646ADGG规格参数

参数名称属性值
是否无铅不含铅
是否Rohs认证符合
厂商名称NXP(恩智浦)
Reach Compliance Codecompliant
其他特性DIRECTION CONTROL; SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED OR REAL TIME DATA
控制类型INDEPENDENT CONTROL
计数方向BIDIRECTIONAL
系列LVT
JESD-30 代码R-PDSO-G56
长度14 mm
逻辑集成电路类型REGISTERED BUS TRANSCEIVER
最大I(ol)0.032 A
湿度敏感等级1
位数8
功能数量2
端口数量2
端子数量56
最高工作温度85 °C
最低工作温度-40 °C
输出特性3-STATE
输出极性TRUE
封装主体材料PLASTIC/EPOXY
封装代码TSSOP
封装等效代码TSSOP56,.3,20
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度)260
电源3.3 V
Prop。Delay @ Nom-Sup3.7 ns
传播延迟(tpd)5.2 ns
认证状态Not Qualified
座面最大高度1.2 mm
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)2.7 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术BICMOS
温度等级INDUSTRIAL
端子面层NICKEL/PALLADIUM/GOLD (NI/PD/AU)
端子形式GULL WING
端子节距0.5 mm
端子位置DUAL
处于峰值回流温度下的最长时间30
翻译N/A
触发器类型POSITIVE EDGE
宽度6.1 mm
Base Number Matches1

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74LVT16646A
3.3 V 16-bit bus transceiver; 3-state
Rev. 03 — 12 January 2005
Product data sheet
1. General description
The 74LVT16646A is a high-performance BiCMOS product designed for V
CC
operation at
3.3 V. This device is a 16-bit transceiver featuring non-inverting 3-state bus compatible
outputs in both send and receive directions. The control function implementation
minimizes external timing requirements. The device features an output enable (OE) input
for easy cascading and a direction (DIR) input for direction control.
Data on bus A or bus B is clocked into the registers on the LOW-to-HIGH transition of the
appropriate clock (CPAB or CPBA). The select control (SAB and SBA) inputs can
multiplex stored and real-time (transparent mode data).
2. Features
s
s
s
s
s
s
s
s
s
s
s
s
16-bit universal bus interface
3-state buffers
Output capability: from +64 mA to
−32
mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
Live insertion and extraction permitted
No bus-current loading when output is tied to 5 V bus
Power-up reset
Power-up 3-state
Latch-up protection exceeds 500 mA per JESD78
ESD protection:
x
MIL STD 883 Method 3 015: exceeds 2000 V
x
Machine model: exceeds 200 V

 
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