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MC74AC646, MC74ACT646
Octal Transceiver/Register
with 3−State Outputs
(Non−inverting)
The MC74AC646/74ACT646 consist of registered bus transceiver
circuits, with outputs, D−type flip−flops and control circuitry
providing multiplexed transmission of data directly from the input bus
or from the internal storage registers. Data on the A or B bus will be
loaded into the respective registers on the LOW−to−HIGH transition
of the appropriate clock pin (CAB or CBA). The four fundamental
data handling functions available are illustrated Figures 1 to 4.
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PDIP−24
N SUFFIX
CASE 724
24
1
24
1
SO−24
DW SUFFIX
CASE 751E
•
•
•
•
•
•
•
w
Independent Registers for A and B Buses
Multiplexed Real−Time and Stored Data Transfers
Choice of True and Inverting Data Paths
3−State Outputs
300 mil Slim Dual In−Line Package
Outputs Source/Sink 24 mA
′ACT646
Has TTL Compatible Inputs
These devices are available in Pb−free package(s). Specifications herein
apply to both standard and Pb−free devices. Please see our website at
www.onsemi.com for specific Pb−free orderable part numbers, or
contact your local ON Semiconductor sales office or representative.
REAL TIME TRANSFER
A-BUS TO B-BUS
A-BUS
REG
B-BUS
REG
REG
B-BUS
REAL TIME TRANSFER
B-BUS TO A-BUS
A-BUS
REG
MARKING DIAGRAMS
PDIP−24
MC74AC646N
AWLYYWW
MC74ACT646N
AWLYYWW
SO−24
AC646
AWLYYWW
Figure 1.
Figure 2.
ACT646
AWLYYWW
STORAGE
FROM BUS TO REGISTER
A-BUS
REG
B-BUS
REG
TRANSFER
FROM REGISTER TO BUS
A-BUS
REG
B-BUS
REG
A
Location
L, WL
Y, YY
W, WW
= Assembly
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
MC74AC646N
MC74ACT646N
MC74AC646DW
MC74AC646DWR
2
MC74ACT646DW
MC74ACT646DWR2
Package
PDIP−24
PDIP−24
SOIC−24
Shipping
15 Units/Rail
15 Units/Rail
30 Units/Rail
Figure 3.
Figure 4.
SOIC−24 1000 Tape & Reel
SOIC−24
30 Units/Rail
SOIC−24 1000 Tape & Reel
©
Semiconductor Components Industries, LLC, 2006
March, 2006
−
Rev. 6
1
Publication Order Number:
MC74AC646/D
MC74AC646, MC74ACT646
V
CC
CBA SBA
24
23
22
G
21
B
0
20
B
1
19
B
2
18
B
3
17
B
4
16
B
5
15
B
6
14
B
7
13
PIN ASSIGNMENT
PIN
A
0
−A
7
B
0
−B
7
CAB, CBA
SAB, SBA
DIR, G
FUNCTION
Data Register Inputs
Data Register A Outputs
Data Register B Inputs
Data Register B Outputs
Clock Pulse Inputs
Transmit/Receive Inputs
Output Enable Inputs
1
2
3
4
A
0
5
A
1
6
A
2
7
A
3
8
A
4
9
A
5
10
A
6
11
A
7
12
GND
CAB SAB DIR
Figure 5. Pinout: 24−Lead Packages Conductors
(Top View)
CAB A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
SAB
DIR
CBA
SBA
G
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
Figure 6. Logic Symbol
G
DIR
CBA
SBA
CAB
SAB
1 OF 8 CHANNELS
D
0
C
0
A
0
B
0
D
0
C
0
TO 7 OTHER CHANNELS
NOTE:
This diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
Figure 7. Logic Diagram
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2
MC74AC646, MC74ACT646
FUNCTION TABLE
Inputs
G
H
H
L
L
L
L
DIR
X
X
L
L
H
H
CAB
H or L
X
X
X
H or L
CBA
H or L
X
X
X
X
SAB
X
X
X
X
L
H
SBA
X
X
L
H
X
X
A
0
−A
7
Input
Output
Input
Data I/O*
B
0
−B
7
Input
Input
Output
Operation or Function
Isolation
Store A and B Data
Real Time B Data to A Bus
Stored B Data to A Bus
Real Time A Data to B Bus
Stored A Data to B Bus
*The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled;
i.e., data at the bus pins will be stored on every LOW−to−HIGH transition of the appropriate clock inputs.
NOTE: H = HIGH Voltage Level; L = LOW Voltage Level; X = Immaterial; = LOW−to−HIGH Transition
MAXIMUM RATINGS*
Symbol
V
CC
V
in
V
out
I
in
I
out
I
CC
T
stg
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Sink/Source Current, per Pin
DC V
CC
or GND Current per Output Pin
Storage Temperature
Value
−0.5
to +7.0
−0.5
to V
CC
+0.5
−0.5
to V
CC
+0.5
±20
±50
±50
−65
to +150
Unit
V
V
V
mA
mA
mA
°C
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recom-
mended Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
, V
out
t
r
, t
f
Supply Voltage
DC Input Voltage, Output Voltage (Ref. to GND)
Input Rise and Fall Time (Note 1)
′AC
Devices except Schmitt Inputs
Input Rise and Fall Time (Note 2)
′ACT
Devices except Schmitt Inputs
Junction Temperature (PDIP)
Operating Ambient Temperature Range
Output Current
−
High
Output Current
−
Low
V
CC
@ 3.0 V
V
CC
@ 4.5 V
V
CC
@ 5.5 V
V
CC
@ 4.5 V
V
CC
@ 5.5 V
Parameter
′AC
′ACT
Min
2.0
4.5
0
−
−
−
−
−
−
−40
−
−
Typ
5.0
5.0
−
150
40
25
10
8.0
−
25
−
−
Max
6.0
5.5
V
CC
−
−
−
−
−
140
85
−24
24
ns/V
°C
°C
mA
mA
ns/V
Unit
V
V
t
r
, t
f
T
J
T
A
I
OH
I
OL
1. V
in
from 30% to 70% V
CC
; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. V
in
from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
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3
MC74AC646, MC74ACT646
DC CHARACTERISTICS
74AC
Symbol
Parameter
V
CC
(V)
T
A
= +25°C
Typ
V
IH
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
V
OL
Maximum Low Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
I
IN
I
OZT
Maximum Input
Leakage Current
Maximum
3-State
Current
†Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
5.5
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
−
−
−
0.002
0.001
0.001
−
−
−
−
74AC
T
A
=
−40°C
to
+85°C
Unit
Conditions
Guaranteed Limits
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
0.1
0.1
0.1
0.36
0.36
0.36
±0.1
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.1
0.1
0.44
0.44
0.44
±1.0
V
V
OUT
= 0.1 V
or V
CC
−
0.1 V
V
OUT
= 0.1 V
or V
CC
−
0.1 V
I
OUT
=
−50
μA
V
IL
V
V
OH
V
V
*V
IN
= V
IL
or V
IH
−12
mA
I
OH
−24
mA
−24
mA
I
OUT
= 50
μA
V
V
*V
IN
= V
IL
or V
IH
12 mA
I
OL
24 mA
24 mA
V
I
= V
CC
, GND
V
I
(OE) = V
IL
, V
IH
V
I
= V
CC
, GND
V
O
= V
CC
, GND
V
OLD
= 1.65 V Max
V
OHD
= 3.85 V Min
V
IN
= V
CC
or GND
μA
5.5
5.5
5.5
5.5
−
−
−
−
±0.6
−
−
8.0
±6.0
75
−75
80
μA
mA
mA
μA
I
OLD
I
OHD
I
CC
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE: I
IN
and I
CC
@ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V
CC
.
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