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MC74AC573, MC74ACT573
Octal Buffer/Line Driver
with 3−State Outputs
The MC74AC573/74ACT573 is a high−speed octal latch with
buffered common Latch Enable (LE) and buffered common Output
Enable (OE) inputs.
The MC74AC573/74ACT573 is functionally identical to the
MC74AC373/74ACT373 but has inputs and outputs on opposite sides.
Features
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•
Inputs and Outputs on Opposite Sides of Package Allowing Easy
•
•
•
•
•
•
Interface with Microprocessors
Useful as Input or Output Port for Microprocessors
Functionally Identical to MC74AC373/74ACT373
3−State Outputs for Bus Interfacing
Outputs Source/Sink 24 mA
′ACT573
Has TTL Compatible Inputs
Pb−Free Packages are Available*
V
CC
20
O
0
19
O
1
18
O
2
17
O
3
16
O
4
15
O
5
14
O
6
13
O
7
12
LE
11
20
1
20
1
MARKING
DIAGRAM
MC74xxx573N
AWLYYWWG
PDIP−20
N SUFFIX
CASE 738
xxx573
AWLYYWWG
SO−20
DW SUFFIX
CASE 751D
1
OE
2
D
0
3
D
1
4
D
2
5
D
3
6
D
4
7
D
5
8
D
6
9
D
7
10
GND
20
1
Figure 1. Pinout 20−Lead Packages Conductors
(Top View)
PIN ASSIGNMENT
PIN
D
0
−D
7
LE
OE
O
0
−O
7
Data Inputs
Latch Enable Input
3−State Output Enable Input
3−State Latch Outputs
20
xxx
573
ALYW
G
G
TSSOP−20
DT SUFFIX
CASE 948E
FUNCTION
74xxx573
AWLYWWG
1
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
LE
OE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
EIAJ−20
M SUFFIX
CASE 967
xxx
= AC or ACT
A
= Assembly Location
WL, L = Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
Figure 2. Logic Symbol
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
©
Semiconductor Components Industries, LLC, 2005
1
September, 2005 − Rev. 7
Publication Order Number:
MC74AC573/D
MC74AC573, MC74ACT573
TRUTH TABLE
Inputs
OE
L
L
L
H
LE
H
H
L
X
D
n
H
L
X
X
Outputs
O
n
H
L
O
0
Z
Functional Description
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O
0
= Previous O
0
before LOW−to−HIGH Transition of Clock
D
0
D
1
D
2
D
3
The MC74AC573/74ACT574 contains eight D−type
latches with 3−state output buffers. When the Latch Enable
(LE) input is HIGH, data on the D
n
inputs enters the latches.
In this condition the latches are transparent, i.e., a latch
output will change state each time its D input changes. When
LE is LOW the latches store the information that was present
on the D inputs a setup time preceding the HIGH−to−LOW
transition of LE. The 3−state buffers are controlled by the
Output Enable (OE) input. When OE is LOW, the buffers are
enabled. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
D
4
D
5
D
6
D
7
D
LE
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
OE
O
0
NOTE:
O
1
O
2
O
3
O
4
O
5
O
6
O
7
That this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
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2
MC74AC573, MC74ACT573
MAXIMUM RATINGS
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
T
stg
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Sink/Source Current, per Pin
DC V
CC
or GND Current per Output Pin
Storage Temperature
Value
−0.5 to +7.0
−0.5 to V
CC
+0.5
−0.5 to V
CC
+0.5
±20
±50
±50
−65 to +150
Unit
V
V
V
mA
mA
mA
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
Supply Voltage
DC Input Voltage, Output Voltage (Ref. to GND)
V
CC
@ 3.0 V
t
r
, t
f
Input Rise and Fall Time (Note 1)
′AC
Devices except Schmitt Inputs
Input Rise and Fall Time (Note 2)
′ACT
Devices except Schmitt Inputs
Junction Temperature (PDIP)
Operating Ambient Temperature Range
Output Current − High
Output Current − Low
V
CC
@ 4.5 V
V
CC
@ 5.5 V
t
r
, t
f
T
J
T
A
I
OH
I
OL
V
CC
@ 4.5 V
V
CC
@ 5.5 V
Parameter
′AC
′ACT
Min
2.0
4.5
0
−
−
−
−
−
−
−40
−
−
Typ
5.0
5.0
−
150
40
25
10
8.0
−
25
−
−
Max
6.0
5.5
V
CC
−
−
−
−
ns/V
−
140
85
−24
24
°C
°C
mA
mA
ns/V
V
V
Unit
1. V
IN
from 30% to 70% V
CC
; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. V
IN
from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
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3
MC74AC573, MC74ACT573
DC CHARACTERISTICS
74AC
Symbol
Parameter
V
CC
(V)
T
A
= +25°C
Typ
V
IH
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
V
OL
Maximum Low Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
I
IN
I
OZ
Maximum Input
Leakage Current
Maximum
3−State
Current
†Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
5.5
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
−
−
−
0.002
0.001
0.001
−
−
−
−
74AC
T
A
=
−40°C to
+85°C
Unit
Conditions
Guaranteed Limits
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
0.1
0.1
0.1
0.36
0.36
0.36
±0.1
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.1
0.1
0.44
0.44
0.44
±1.0
V
V
OUT
= 0.1 V
or V
CC
− 0.1 V
V
OUT
= 0.1 V
or V
CC
− 0.1 V
I
OUT
= −50
mA
V
*V
IN
= V
IL
or V
IH
−12 mA
I
OH
−24 mA
−24 mA
I
OUT
= 50
mA
V
*V
IN
= V
IL
or V
IH
12 mA
I
OL
24 mA
24 mA
V
I
= V
CC
, GND
V
I
(OE) = V
IL
, V
IH
V
I
= V
CC
, GND
V
O
= V
CC
, GND
V
OLD
= 1.65 V Max
V
OHD
= 3.85 V Min
V
IN
= V
CC
or GND
V
IL
V
V
OH
V
V
mA
5.5
5.5
5.5
5.5
−
−
−
−
±0.5
−
−
8.0
±5.0
75
−75
80
mA
mA
mA
mA
I
OLD
I
OHD
I
CC
NOTE: I
IN
and I
CC
@ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V
CC
.
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
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