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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4007UB
gates
Dual complementary pair and
inverter
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
Dual complementary pair and inverter
DESCRIPTION
HEF4007UB
gates
The HEF4007UB is a dual complementary pair and an inverter with access to each device. It has three n-channel and
three p-channel enhancement mode MOS transistors.
Fig.1 Schematic diagram.
PINNING
S
P2
, S
P3
D
P1
, D
P2
D
N1
, D
N2
S
N2
, S
N3
Fig.2 Pinning diagram.
D
N/P3
G
1
to G
3
HEF4007UBP(N):
HEF4007UBD(F):
HEF4007UBT(D):
14-lead DIL; plastic
(SOT27-1)
14-lead DIL; ceramic (cerdip)
(SOT73)
14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
FAMILY DATA, I
DD
LIMITS category GATES
See Family Specifications for V
IH
/V
IL
unbuffered stages
source connections to 2nd and 3rd
p-channel transistors
drain connections from the 1st and 2nd
p-channel transistors
drain connections from the 1st and 2nd
n-channel transistors
source connections to the 2nd and 3rd
n-channel transistors
common connection to the 3rd p-channel
and n-channel transistor drains
gate connections to n-channel and
p-channel of the three transistor pairs
January 1995
2
Philips Semiconductors
Product specification
Dual complementary pair and inverter
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°C;
C
L
= 50 pF; input transition times
≤
20 ns
V
DD
V
Propagation delays
G
n
→
D
N
; D
P
HIGH to LOW
5
10
15
5
LOW to HIGH
Output transition times
HIGH to LOW
10
15
5
10
15
5
LOW to HIGH
10
15
t
TLH
t
THL
t
PLH
t
PHL
40
20
15
40
20
15
60
30
20
60
30
20
80
40
30
75
40
30
120
60
40
120
60
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
TYP.
MAX.
HEF4007UB
gates
TYPICAL EXTRAPOLATION
FORMULA
13 ns + (0,55 ns/pF) C
L
9 ns + (0,23 ns/pF) C
L
7 ns + (0,16 ns/pF) C
L
13 ns + (0,55 ns/pF) C
L
9 ns + (0,23 ns/pF) C
L
7 ns + (0,16 ns/pF) C
L
10 ns + (1,0 ns/pF) C
L
9 ns + (0,42 ns/pF) C
L
6 ns + (0,28 ns/pF) C
L
10 ns + (1,0 ns/pF) C
L
9 ns + (0,42 ns/pF) C
L
6 ns + (0,28 ns/pF) C
L
V
DD
V
Dynamic power
dissipation per
package (P)
5
10
15
TYPICAL FORMULA FOR P (µW)
4500 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
20 000 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
50 000 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
where
f
i
= input freq. (MHz)
f
o
= output freq. (MHz)
C
L
= load capacitance (pF)
∑(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
January 1995
3
Philips Semiconductors
Product specification
Dual complementary pair and inverter
HEF4007UB
gates
Fig.3
Typical drain current I
D
and output voltage V
O
as
functions of input voltage; V
DD
= 5 V; T
amb
= 25
°C.
Fig.4
Typical drain current I
D
and output voltage V
O
as
functions of input voltage; V
DD
= 10 V; T
amb
= 25
°C.
Fig.5
Typical drain current I
D
and output voltage V
O
as
functions of input voltage; V
DD
= 15 V; T
amb
= 25
°C.
January 1995
4
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