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74F552 Octal Registered Transceiver with Parity and Flags
April 1988
Revised March 2000
74F552
Octal Registered Transceiver with Parity and Flags
General Description
The 74F552 octal transceiver contains two 8-bit registers
for temporary storage of data flowing in either direction.
Each register has its own clock pulse and clock enable
input as well as a flag flip-flop that is set automatically as
the register is loaded. The flag output will be reset when
the output enable returns to HIGH after reading the output
port. Each register has a separate output enable control for
its 3-STATE buffer. The separate Clocks, Flags, and
Enables provide considerable flexibility as I/O ports for
demand-response data transfer. When data is transferred
from the A Port to the B Port, a parity bit is generated. On
the other hand, when data is transferred from the B Port to
the A Port, the parity of input data on B
0
–B
7
is checked.
Features
s
8-Bit bidirectional I/O Port with handshake
s
Register status flag flip-flops
s
Separate clock enable and output enable
s
Parity generation and parity check
s
B-outputs sink 64 mA
s
3-STATE outputs
Ordering Code:
Order Number
74F552SC
74F552QC
Package Number
M28B
V28A
Package Description
28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for SOIC
Pin Assignments for PLCC
© 2000 Fairchild Semiconductor Corporation
DS009561
www.fairchildsemi.com
74F552
Logic Symbols
IEEE/IEC
Unit Loading/Fan Out
Pin Names
A
0
–A
7
B
0
–B
7
FR
FS
PARITY
ERROR
CER
CES
CPR
CPS
OEBR
OEAS
Description
A-to-B Port Data Inputs or
B-to-A 3-STATE
B-to-A Transceiver Inputs or
A-to-B 3-STATE Output
B Port Flag Output
A Port Flag Output
Parity Bit Transceiver Input or Output
Parity Check Output (Active LOW)
R Registers Clock Enable Input (Active LOW)
S Registers Clock Enable Input (Active LOW)
R Registers Clock Pulse Input (Active Rising Edge)
S Registers Clock Pulse Input (Active Rising Edge)
B Port and PARITY Output Enable (Active LOW)
and Clear FR Input (Active Rising Edge)
A Port Output Enable (Active LOW)
and Clear FS Input (Active Rising Edge)
1.0/2.0
20
µA/−1.2
mA
U.L.
HIGH/LOW
3.5/1.083
150/40 (33.3)
3.5/1.083
50/33.3
50/33.3
3.5/1.083
50/33.3
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/2.0
Input I
IH
/I
IL
Output I
OH
/I
OL
70
µA/−0.65
mA
−3
mA/24 mA (20 mA)
70
µA/−0.65
mA
−1
mA/20 mA
−1
mA/20 mA
70
µA/−0.65
mA
−1
mA/20 mA
20
µA/−0.6
mA
20
µA/−0.6
mA
20
µA/−0.6
mA
20
µA/−0.6
mA
20
µA/−1.2
mA
600/106.6 (80)
−12
mA/64 mA (48 mA)
600/106.6 (50)
−12
mA/64 mA (48 mA)
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2
74F552
Functional Description
Data applied to the A-inputs are entered and stored in the
R register on the rising edge of the CPR Clock Pulse, pro-
vided that the Clock Enable (CER) is LOW; simultaneously,
the status flip-flop is set and the flag (FR) output goes
HIGH. As the Clock Enable (CER) returns to HIGH, the
data will be held in the R register. These data entered from
the A-inputs will appear at the B Port I/O pins after the Out-
put Enable (OEBR) has gone LOW. When OEBR is LOW,
a parity bit appears at the PARITY pin, which will be set
HIGH when there is an even number of 1s or all 0s at the Q
outputs of the R register. After the data is assimilated, the
receiving system clears the flag FR by changing the signal
at the OEBR pin from LOW-to-HIGH.
Data flow from B-to-A proceeds in the same manner
described for A-to-B flow. A LOW at the CES pin and a
LOW-to-HIGH transition at CPS pin enters the B-input data
and the parity-input data into the S registers and the parity
register respectively and set the flag output FS to HIGH. A
LOW signal at the OEAS pin enables the A Port I/O pins
and a LOW-to-HIGH transition of the OEAS signal clears
the FS flag. When OEAS is LOW, the parity check output
ERROR will be HIGH if there is an odd number of 1s at the
Q outputs of the S registers and the parity register. The flag
FS can be cleared by a LOW-to-HIGH transition of the
OEAS signal.
Register Function Table
(Applies to R or S Register)
Inputs
D
X
L
H
X
CP
CE
H
L
L
L
Internal
Function
Q
NC
L
H
NC
Hold Data
Load Data
Keep Old Data
Flag Flip-Flop Function Table
(Applies to R or S Flag Flip-Flop)
Inputs
Flag
Function
CE
H
L
X
CP
OE
†
Output
NC
H
L
Hold Flag
Set Flag
Clear Flag
X
†
X
X
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Transition
†
=
Not LOW-to-HIGH Transition
NC
=
No Change
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
†
=
LOW-to-HIGH Transition
†
=
Not LOW-to-HIGH Transition
NC
=
No Change
Output Control
OE
H
L
L
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Parity Generation Function
A or B
Outputs
Z
L
H
Function
Disable Output
Enable Output
Enable Output
OEBR
H
L
L
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Internal
Q
X
L
H
Number of HIGHs in the
Q Outputs of the R Register
X
0, 2, 4, 6, 8
1, 3, 5, 7
X
=
Immaterial
Z
=
High Impedance
Parity Output
Z
H
L
X
=
Immaterial
Z
=
High Impedance
Parity Check Function
OEAS
H
L
L
L
L
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Number of HIGHs in
the Q Outputs of the S Register
X
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
Parity
Input
X
L
L
H
H
ERROR
Output
H
L
H
H
L
3
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74F552
Block Diagram
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4
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