74VHC373
•
74VHCT373 Octal D-Type Latch with 3-STATE Outputs
January 1998
74VHC373
•
74VHCT373
Octal D-Type Latch with 3-STATE Outputs
General Description
The VHC/VHCT373 is an advanced high speed CMOS octal
D-type latch with 3-STATE output fabricated with silicon gate
CMOS technology. It achieves the high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining
the CMOS low power dissipation. This 8-bit D-type latch is
controlled by a latch enable input (LE) and an output enable
input (OE). The latches appear transparent to data when
latch enable (LE) is HIGH. When LE is low, the data that
meets the setup time is latched. When the OE input is high,
the eight outputs are in a high impedance state.
An input protection circuit ensures that 0V–7V can be ap-
plied to the input pins without regard to the supply voltage.
This device can be used to interface 5V to 3V systems and
two supply systems such as battery back up. This circuit pre-
vents device destruction due to mismatched supply and in-
put voltages.
Features
n
High Speed:
VHC t
pd
= 5.0 ns (typ)
@
V
CC
= 5V
VHCT t
pd
= 5.1 ns (typ)
@
V
CC
= 5V
n
High Noise Immunity:
VHC V
NIH
= V
NIL
= 28% V
CC
(Min)
VHCT V
IH
= 2.0V, V
IL
= 0.8V
n
Power Down Protection:
VHC Inputs Only
VHCT Inputs and Outputs
n
Low Noise:
VHC V
OLP
= 0.6V (typ)
VHCT V
OLP
= 0.8V (typ)
n
Low Power Dissipation:
I
CC
= 4 µA (Max)
@
T
a
= 25˚C
n
Pin and Function Compatible with 74HC/HCT373
Ordering Code:
Commercial
74VHC373M
74VHC373SJ
74VHC373MTC
74VHC373N
74VHCT373M
74VHCT373SJ
74VHCT373MTC
74VHCT373N
Package Number
M20B
M20D
MTC20
N20A
M20B
M20D
MTC20
N20A
Package Description
20-Lead Molded JEDEC SOIC
20-Lead Molded EIAJ SOIC
20-Lead Molded JEDEC Type 1 TSSOP
20-Lead Molded DIP
20-Lead Molded JEDEC SOIC
20-Lead Molded EIAJ SOIC
20-Lead Molded JEDEC Type 1 TSSOP
20-Lead Molded DIP
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Assignment for
DIP,TSSOP and SOIC
DS011555-1
DS011555-2
© 1998 Fairchild Semiconductor Corporation
DS011555
www.fairchildsemi.com
Pin Descriptions
Pin
Names
D
0
–D
7
LE
OE
O
0
–O
7
Description
Truth Table
Inputs
LE
OE
H
L
L
L
D
n
X
L
H
X
X
H
H
L
Outputs
O
n
Z
L
H
O
0
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Outputs
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O
0
= Previous O
0
before HIGH to Low transition of Latch Enable
Functional Description
The VHC/VHCT373 contains eight D-type latches with
3-STATE standard outputs. When the Latch Enable (LE) in-
put is HIGH, data on the D
n
inputs enters the latches. In this
condition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW tran-
sition of LE. The 3-STATE standard outputs are controlled by
the Output Enable (OE) input. When OE is LOW, the stan-
dard outputs are in the 2-state mode. When OE is HIGH, the
standard outputs are in the high impedance mode but this
does not interfere with entering new data into the latches.
Logic Diagram
DS011555-3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
VHC
VHCT (Note 2)
Input Diode Current (I
IK
)
Output Diode Current (VHC)
(VHCT)
DC Output Current (I
OUT
)
DC V
CC
/GND Current (I
CC
)
Storage Temperature (T
STG
)
Lead Temperature (T
L
)
(Soldering, 10 sec)
−0.5V to + 7.0V
−0.5V to + 7.0V
−0.5V to V
CC
+ 0.5V
−0.5V to +7.0V
−20 mA
±
20 mA
−20 mA
±
25 mA
±
75 mA
−65˚C to +150˚C
260˚C
Recommended Operating
Conditions
(Note 3)
Supply Voltage (V
CC
)
VHC
VHCT
Input Voltage (V
IN
)
Output Voltage (V
OUT
)
Operating Temperature (T
OPR
)
VHC/VHCT
Input Rise and Fall Time (t
r
, t
f
)
V
CC
= 3.3V
±
0.3V (VHC only)
V
CC
= 5.0
±
0.5V
2.0V to
4.5V to
0V to
0V
+ 5.5V
+ 5.5V
+ 5.5V
to V
CC
−40˚C to +85˚C
0
z
100 ns/V
0
z
20 ns/V
Note 1:
Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifications
should be met, without exception, to ensure that the system design is reliable
over its power supply, temperature, and output/input loading variables. Fair-
child does not recommend operation outside databook specifications.
Note 2:
V
OUT
>
V
CC
only if output is in H or Z state.
Note 3:
Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics for VHC
Symbol
V
IH
V
IL
V
OH
Parameter
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
V
CC
(V)
2.0
3.0−5.5
2.0
3.0−5.5
2.0
3.0
4.5
3.0
4.5
V
OL
Low Level Output
Voltage
2.0
3.0
4.5
3.0
4.5
I
OZ
I
IN
I
CC
3-STATE Output
Off-State Current
Input Leakage
Current
Quiescent Supply
Current
5.5
0−5.5
5.5
1.9
2.9
4.4
2.58
3.94
0.0
0.0
0.0
0.1
0.1
0.1
0.36
0.36
2.0
3.0
4.5
T
A
= +25˚C
Min
1.50
0.7 V
CC
0.50
0.3 V
CC
1.9
2.9
4.4
2.48
3.80
0.1
0.1
0.1
0.44
0.44
V
µA
µA
µA
I
OL
= 4 mA
I
OL
= 8 mA
V
IN
= V
IH
or V
IL
V
OUT
= V
CC
or GND
V
IN
= 5.5 or GND
V
IN
= V
CC
or GND
V
V
IN
= V
IH
or V
IL
V
I
OH
= −4 mA
I
OH
= −8 mA
I
OL
= 50 µA
V
Typ
Max
T
A
= −40˚C
to +85˚C
Min
1.50
0.7 V
CC
0.50
0.3 V
CC
V
IN
= V
IH
or V
IL
I
OH
= −50 µA
V
Max
V
Units
Conditions
±
0.25
±
0.1
4.0
±
2.5
±
1.0
40.0
Noise Characteristics for VHC
Symbol
V
OLP
(Note 4)
V
OLV
(Note 4)
V
IHD
(Note 4)
V
ILD
(Note 4)
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
CC
(V)
5.0
5.0
5.0
5.0
T
A
= +25˚C
Typ
0.6
−0.6
Limits
0.9
−0.9
3.5
1.5
V
V
V
V
C
L
= 50 pF
C
L
= 50 pF
C
L
= 50 pF
C
L
= 50 pF
Units
Conditions
Note 4:
Parameter guaranteed by design.
3
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DC Electrical Characteristics for VHCT
Symbol
Parameter
V
CC
(V)
Min
V
IH
V
IL
V
OH
V
OL
I
OZ
I
IN
I
CC
I
CCT
I
OFF
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
3-STATE Output Off-State Current
Input Leakage Current
Quiescent Supply Current
Maximum I
CC
/Input
Output Leakage Current (Power
Down State)
4.5
5.5
4.5
5.5
4.5
4.5
4.5
4.5
5.5
0–5.5
5.5
5.5
0.0
3.15
2.5
0.0
0.1
0.36
3.65
2.0
2.0
0.8
0.8
3.15
2.4
0.1
0.44
T
A
= +25˚C
Typ
Max
T
A
= −40˚C
to +85˚C
Min
2.0
2.0
0.8
0.8
V
V
V
V
µA
µA
µA
mA
µA
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OH
= −50 µA
I
OH
= −8 mA
I
OL
= 50 µA
I
OL
= 8 mA
V
Max
V
Units
Conditions
±
0.25
±
0.1
4.0
1.35
+0.5
±
2.5
±
1.0
40.0
1.50
+0.5
V
IN
= V
IH
or V
IL
V
OUT
= V
CC
or GND
V
IN
= 5.5V or GND
V
IN
= V
CC
or GND
V
IN
= 3.4V
Other Inputs = V
CC
or GND
V
OUT
= 5.5V
Noise Characteristics for VHCT
Symbol
V
OLP
V
OLV
V
IHD
V
ILD
(Note 5)
(Note 5)
(Note 5)
(Note 5)
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
CC
(V)
5.0
5.0
5.0
5.0
T
A
= +25˚C
Typ
0.8
−0.8
Limits
1.2
−1.2
2.0
0.8
V
V
V
V
C
L
= 50 pF
C
L
= 50 pF
C
L
= 50 pF
C
L
= 50 pF
Units
Conditions
Note 5:
Parameter guaranteed by design.
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4
AC Electrical Characteristics for VHC
V
CC
(V)
Min
t
PLH
t
PHL
Propagation Delay
Time (LE to O
n
)
3.3
±
0.3
5.0
±
0.5
t
PLH
t
PHL
Propagation Delay
Time (D to O
n
)
3.3
±
0.3
5.0
±
0.5
t
PZL
t
PZH
3-STATE
Output
Enable Time
t
PLZ
t
PHZ
t
OSLH
t
OSHL
C
IN
C
OUT
C
PD
3-STATE Output
Disable Time
Output to Output
Skew
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance
5.0
±
0.5
3.3
±
0.3
5.0
±
0.5
3.3
±
0.3
5.0
±
0.5
4
6
27
3.3
±
0.3
T
A
= +25˚C
Typ
7.0
9.5
4.9
6.4
7.3
9.8
5.0
6.5
7.3
9.8
5.5
7.0
9.5
6.5
Max
11.0
14.5
7.2
9.2
11.4
14.9
7.2
9.2
11.4
14.9
8.1
10.1
13.2
9.2
1.5
1.0
10
T
A
= −40˚C
to +85˚C
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
13.0
16.5
8.5
10.5
13.5
17.0
8.5
10.5
13.5
17.0
9.5
11.5
15.0
10.5
1.5
1.0
10
pF
pF
pF
V
CC
= Open
V
CC
= 5.0V
(Note 7)
ns
(Note 6)
ns
R
L
= 1 kΩ
ns
ns
R
L
= 1 kΩ
ns
ns
ns
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 50 pF
C
L
= 50 pF
C
L
= 50 pF
C
L
= 50 pF
Symbol
Parameter
Units
Conditions
Note 6:
Parameter guaranteed by design. t
OSLH
= |t
PLH max
− t
PLH min
|; t
OSHL
= |t
PHL max
− t
PHL
min|
Note 7:
C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average oper-
ating current can be obtained by the equation: I
CC
(opr.) = C
PD
•
V
CC
•
f
IN
+ I
CC
/8 (per Latch). The total C
PD
when n pcs. of the Latch operates can be calculated
by the equation: C
PD
(total) = 14 + 13n.
AC Operating Requirements for VHC
V
CC
(V)
Min
t
W(H)
t
S
t
H
Minimum Pulse
Width (LE)
Minimum Set-Up
Time
Minimum Hold
Time
3.3
±
0.3
5.0
±
0.5
3.3
±
0.3
5.0
±
0.5
3.3
±
0.3
5.0
±
0.5
5.0
5.0
4.0
4.0
1.0
1.0
T
A
= +25˚C
Typ
Max
Min
5.0
5.0
4.0
4.0
1.0
1.0
ns
ns
T
A
= −40˚C
to +85˚C
Max
ns
Symbol
Parameter
Units
5
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