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74AC574 • 74ACT574 Octal D-Type Flip-Flop with 3-STATE Outputs
September 1988
Revised March 2005
74AC574 • 74ACT574
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The AC/ACT574 is a high-speed, low power octal flip-flop
with a buffered common Clock (CP) and a buffered com-
mon Output Enable (OE). The information presented to the
D-type inputs is stored in the flip-flops on the LOW-to-HIGH
Clock (CP) transition.
The AC/ACT574 is functionally identical to the AC/ACT374
except for the pinouts.
Features
s
I
CC
and I
OZ
reduced by 50%
s
Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
s
Useful as input or output port for microprocessors
s
Functionally identical to AC/ACT374
s
3-STATE outputs for bus-oriented applications
s
Outputs source/sink 24 mA
s
ACT574 has TTL-compatible inputs
Ordering Code:
Order Number
74AC574SC
74AC574SJ
74AC574MTC
74AC574PC
74ACT574SC
74ACT574SJ
74ACT574MTC
74ACT574PC
Package Number
M20B
M20D
MTC20
N20A
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
FACT
¥
is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS009910
www.fairchildsemi.com
74AC574 • 74ACT574
Logic Symbols
Pin Descriptions
Pin Names
D
0
–D
7
CP
OE
O
0
–O
7
Data Inputs
Clock Pulse Input
3-STATE Output Enable Input
3-STATE Outputs
Description
IEEE/IEC
Function Table
Inputs
OE
H
H
H
H
L
L
L
CP D
H
L
H
L
H
L
H
L
H
Internal
Q
NC
NC
L
H
L
H
NC
NC
Outputs
O
N
Z
Z
Z
Z
L
H
NC
NC
Hold
Hold
Load
Load
Data Available
Data Available
No Change in Data
No Change in Data
Function
H
H
H
Connection Diagram
L
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
LOW-to-HIGH Transition
NC No Change
Functional Description
The AC/ACT574 consists of eight edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The buffered clock and buffered Output Enable are com-
mon to all flip-flops. The eight flip-flops will store the state
of their individual D-type inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CP)
transition. With the Output Enable (OE) LOW, the contents
of the eight flip-flops are available at the outputs. When OE
is HIGH, the outputs go to the high impedance state. Oper-
ation of the OE input does not affect the state of the flip-
flops.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2
74AC574 • 74ACT574
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
V
I
0.5V to
7.0V
20 mA
20 mA
0.5V to V
CC
0.5V
20 mA
20 mA
0.5V to V
CC
0.5V
r
50 mA
r
50 mA
65
q
C to
150
q
C
140
q
C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
AC
ACT
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (
'
V/
'
t)
AC Devices
V
IN
from 30% to 70% of V
CC
V
CC
@ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (
'
V/
'
t)
ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
125 mV/ns
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT
¥
circuits outside databook specifications.
0.5V
V
CC
0.5V
2.0V to 6.0V
4.5V to 5.5V
0V to V
CC
0V to V
CC
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
V
O
0.5V
V
CC
0.5V
40
q
C to
85
q
C
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
Per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
Junction Temperature (T
J
)
PDIP
125 mV/ns
DC Electrical Characteristics for AC
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
CC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
I
IN
(Note 4)
I
OZ
Maximum Input Leakage Current
Maximum
3-STATE
Leakage Current
I
OLD
I
OHD
I
CC
(Note 4)
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent Supply Current
5.5
5.5
5.5
4.0
75
mA
mA
5.5
5.5
0.002
0.001
0.001
T
A
Typ
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
0.1
0.1
0.1
0.36
0.36
0.36
25
q
C
T
A
40
q
C to
85
q
C
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.1
0.1
Guaranteed Limits
Units
V
OUT
V
Conditions
0.1V
or V
CC
0.1V
V
OUT
0.1V
V
or V
CC
0.1V
V
I
OUT
V
IN
50
P
A
V
IL
or V
IH
V
I
OH
I
OH
I
OH
12 mA
24 mA I
OH
24 mA (Note 2)
50
P
A
V
IL
or V
IH
12 mA
24 mA
24 mA (Note 2)
V
CC
, GND
V
IL
, V
IH
V
CC
, V
GND
V
CC
, GND
1.65V
3.85V
V
CC
or GND
V
I
OUT
V
IN
0.44
0.44
0.44
V
I
OL
I
OL
I
OL
V
I
V
I
V
O
V
OLD
V
OHD
V
IN
r
0.1
r
0.25
r
1.0
r
2.5
P
A
P
A
V
I
(OE)
75
40.0
P
A
Note 2:
All outputs loaded; thresholds on input associated with output under test.
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 4:
I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
3
www.fairchildsemi.com
74AC574 • 74ACT574
DC Electrical Characteristics for ACT
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum HIGH Level
Input Voltage
Maximum LOW Level
Input Voltage
Minimum HIGH Level
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
4.5
5.5
4.5
5.5
I
IN
I
OZ
I
CCT
I
]OLD
I
OHD
I
CC
Maximum Input
Leakage Current
Maximum 3-STATE
Leakage Current
Maximum I
CC
/Input
Minimum Dynamic
Output Current (Note 6)
Maximum Quiescent
Supply Current
5.5
5.5
5.5
5.5
5.5
5.5
4.0
0.6
0.001
0.001
T
A
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
25
q
C
T
A
40
q
C to
85
q
C
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
Guaranteed Limits
Units
V
V
V
V
OUT
V
OUT
Conditions
0.1V
0.1V
or V
CC
0.1V
or V
CC
0.1V
I
OUT
V
IN
50
P
A
V
IL
or V
IH
V
I
OH
I
OH
24 mA
24 mA (Note 5)
50
P
A
V
IL
or V
IH
24 mA
24 mA (Note 5)
V
CC
, GND
V
IL
, V
IH
V
CC
, GND
V
CC
2.1V
1.65V
3.85V
V
CC
V
I
OUT
V
IN
V
I
OL
I
OL
r
0.1
r
0.25
r
1.0
r
2.5
1.5
75
P
A
P
A
mA
mA
mA
V
I
V
I
V
O
V
I
V
OLD
V
OHD
V
IN
75
40.0
P
A
or GND
Note 5:
All outputs loaded; thresholds on input associated with output under test.
Note 6:
Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
V
CC
Symbol
f
MAX
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Parameter
Maximum Clock
Frequency
Propagation Delay
CP to O
n
Propagation Delay
CP to O
n
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
(V)
(Note 7)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
Note 7:
Voltage Range 3.3 is 3.3V
r
0.3V
Voltage Range 5.0 is 5.0V
r
0.5V
T
A
C
L
Min
75
95
3.5
2.0
3.5
2.0
2.5
2.0
3.0
2.0
3.5
2.0
2.0
1.0
25
q
C
50 pF
Typ
112
153
8.5
6.0
7.5
5.5
7.0
5.0
6.5
5.0
7.5
6.0
5.5
4.5
13.5
9.5
12.0
8.5
11.0
8.5
10.5
8.0
12.0
9.5
9.0
7.5
Max
T
A
40
q
C to
85
q
C
C
L
50 pF
Max
MHz
15.0
11.0
13.5
9.5
12.0
9.0
11.5
9.0
13.0
10.5
10.0
8.5
ns
ns
ns
ns
ns
ns
Units
Min
60
85
3.5
2.0
3.5
2.0
2.5
2.0
3.0
1.5
2.5
1.5
1.5
1.0
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