74AC574
•
74ACT574 Octal D-Type Flip-Flop with 3-STATE Outputs
May 1998
74AC574
•
74ACT574
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The AC/ACT574 is a high-speed, low power octal flip-flop
with a buffered common Clock (CP) and a buffered common
Output Enable ( OE). The information presented to the
D-type inputs is stored in the flip-flops on the LOW-to-HIGH
Clock (CP) transition.
The AC/ACT574 is functionally identical to the AC/ACT374
except for the pinouts.
Features
n
I
CC
and I
OZ
reduced by 50%
n
Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
n
Useful as input or output port for microprocessors
n
Functionally identical to AC/ACT374
n
3-STATE outputs for bus-oriented applications
n
Outputs source/sink 24 mA
n
ACT574 has TTL-compatible inputs
Ordering Code:
Order Number
74AC574PC
74AC574SC
74AC574SJ
74ACT574PC
74ACT574SC
74ACT574SJ
74ACT574MTC
Package Number
V20A
M20B
M20D
V20A
M20B
M20D
MTC20
Package Description
20-Lead Molded Dual-in-Line Package
20-Lead (0.300" Wide) Molded Small Outline Package, JEDEC
20-Lead Molded Shrink Small Outline Package, EIAJ Type II
20-Lead Molded Dual-in-Line Package
20-Lead (0.300" Wide) Molded Small Outline Package, JEDEC
20-Lead Molded Shrink Small Outline Package, EIAJ Type II
20-Lead Thin Shrink Small Outline Package, JEDEC
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagrams
Pin Assignment for DIP,
SOIC and TSSOP
DS009910-1
IEEE/IEC
DS009910-2
Pin Descriptions
Pin Names
D
0
–D
7
CP
DS009910-4
Description
Data Inputs
Clock Pulse Input
3-STATE Output Enable Input
3-STATE Outputs
OE
O
0
–O
7
FACT
™
is a trademark of Fairchild Semiconductor Corporation.
© 1998 Fairchild Semiconductor Corporation
DS009910
www.fairchildsemi.com
Functional Description
The AC/ACT574 consists of eight edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Output Enable are common to all
flip-flops. The eight flip-flops will store the state of their indi-
vidual D-type inputs that meet the setup and hold time re-
quirements on the LOW-to-HIGH Clock (CP) transition. With
the Output Enable (OE) LOW, the contents of the eight
flip-flops are available at the outputs. When OE is HIGH, the
outputs go to the high impedance state. Operation of the OE
input does not affect the state of the flip-flops.
Function Table
Inputs
OE
H
H
H
H
L
L
L
L
CP
H
H
N
N
N
N
Internal Outputs
D
L
H
L
H
L
H
L
H
Q
NC
NC
L
H
L
H
NC
NC
O
N
Z
Z
Z
Z
L
H
NC
NC
Hold
Hold
Load
Load
Function
Data Available
Data Available
No Change in Data
No Change in Data
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
N
= LOW-to-HIGH Transition
NC = No Change
Logic Diagram
DS009910-5
Please note that this diagram is provided only for the understanding of
logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −0.5V
V
I
= V
CC
+0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −0.5V
V
O
= V
CC
+0.5V
DC Output Voltage (V
O
)
DC Output Source or Sink Current
(I
O
)
DC V
CC
or Ground Current
Per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
Junction Temperature (T
J
)
PDIP
−0.5V to +7.0V
−20 mA
+20 mA
−0.5V to V
CC
+0.5V
−20 mA
+20 mA
−0.5V to V
CC
+0.5V
Recommended Operating
Conditions
Supply Voltage (V
CC
)
(Unless Otherwise Specified)
(AC)
(ACT)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (∆V/∆t)
AC Devices
V
IN
from 30% to 70% of V
CC
V
CC
@
3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (∆V/∆t)
ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V
2.0V to 6.0V
4.5V to 5.5V
0V to V
CC
0V to V
CC
−40˚C to +85˚C
±
50 mA
±
50 mA
−65˚C to +150˚C
140˚C
125 mV/ns
125 mV/ns
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. Fairchild does not recom-
mend operation of FACT
™
circuits outside databook specifications.
DC Electrical Characteristics for AC
Symbol
Parameter
V
CC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
V
OL
Maximum Low
Level Output
Voltage
3.0
4.5
5.5
3.0
4.5
5.5
I
IN
(Note 4)
I
OZ
Maximum Input
Leakage Current
Maximum
3-STATE
Leakage Current
I
OLD
I
OHD
I
CC
(Note 4)
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
5.5
5.5
5.5
4.0
75
−75
40.0
mA
mA
µA
5.5
V
I
(OE) = V
IL
, V
IH
5.5
0.002
0.001
0.001
T
A
= 25˚C
Typ
V
IH
Minimum High
Level Input
Voltage
V
IL
Maximum Low
Level Input
Voltage
V
OH
Minimum High
Level Output
Voltage
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
0.1
0.1
0.1
0.36
0.36
0.36
T
A
= −40˚C to +85˚C
Guaranteed Limits
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.1
0.1
V
IN
= V
IL
or V
IH
0.44
0.44
0.44
V
µA
I
OL
= 12 mA
I
OL
= 24 mA
I
OL
= 24 mA (Note 2)
V
I
= V
CC
, GND
V
V
V
IN
= V
IL
or V
IH
I
OH
= −12 mA
I
OH
= −24 mA I
OH
I
OH
= −24 mA (Note 2)
I
OUT
= 50 µA
V
I
OUT
= −50 µA
V
V
OUT
= 0.1V
or V
CC
− 0.1V
V
V
OUT
= 0.1V
or V
CC
− 0.1V
Units
Conditions
±
0.1
±
1.0
±
0.25
±
2.5
µA
V
I
= V
CC
, V
GND
V
O
= V
CC
, GND
V
OLD
= 1.65V
V
OHD
= 3.85V
V
IN
= V
CC
or GND
Note 2:
All outputs loaded; thresholds on input associated with output under test.
3
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DC Electrical Characteristics for AC
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
(Continued)
Note 4:
I
IN
and I
CC
@
3.0V are guaranteed to be less than or equal to the respective limit
@
5.5V V
CC
.
DC Electrical Characteristics for ACT
Symbol
Parameter
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum Low Level
Output Voltage
4.5
5.5
4.5
5.5
I
IN
I
OZ
I
CCT
I
]OLD
I
OHD
I
CC
Maximum Input
Leakage Current
Maximum 3-STATE
Leakage Current
Maximum I
CC
/Input
Minimum
Dynamic Output
Current (Note 6)
Maximum Quiescent
Supply Current
Note 5:
All outputs loaded; thresholds on input associated with output under test.
Note 6:
Maximum test duration 2.0 ms, one output loaded at a time.
T
A
= 25˚C
Typ
T
A
= −40˚C to +85˚C
Guaranteed Limits
Units
Conditions
V
IH
V
IL
V
OH
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
2.0
2.0
0.8
0.8
4.4
5.4
V
V
V
V
OUT
= 0.1V
or V
CC
− 0.1V
V
OUT
= 0.1V
or V
CC
− 0.1V
I
OUT
= −50 µA
V
IN
= V
IL
or V
IH
3.76
4.76
0.1
0.1
V
V
I
OH
= −24 mA
I
OH
= −24 mA (Note 5)
I
OUT
= 50 µA
V
IN
= V
IL
or V
IH
0.001
0.001
0.1
0.1
0.36
0.36
0.44
0.44
V
µA
µA
mA
mA
mA
µA
I
OL
= 24 mA
I
OL
= 24 mA (Note 5)
V
I
= V
CC
, GND
V
I
= V
IL
, V
IH
V
O
= V
CC
, GND
V
I
= V
CC
− 2.1V
V
OLD
= 1.65V
V
OHD
= 3.85V
V
IN
= V
CC
or GND
5.5
5.5
5.5
5.5
5.5
5.5
0.6
±
0.1
±
0.25
±
1.0
±
2.5
1.5
75
−75
4.0
40.0
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4
AC Electrical Characteristics for AC
T
A
= −40˚C to +85˚C
C
L
= 50 pF
Max
Min
60
85
13.5
9.5
12.0
8.5
11.0
8.5
10.5
8.0
12.0
9.5
9.0
7.5
3.5
2.0
3.5
2.0
2.5
2.0
3.0
1.5
2.5
1.5
1.5
1.0
15.0
11.0
13.5
9.5
12.0
9.0
11.5
9.0
13.0
10.5
10.0
8.5
ns
ns
ns
ns
ns
ns
Max
MHz
Symbol
Parameter
V
CC
(V)
(Note 7)
Min
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
75
95
3.5
2.0
3.5
2.0
2.5
2.0
3.0
2.0
3.5
2.0
2.0
1.0
T
A
= +25˚C
C
L
= 50 pF
Typ
112
153
8.5
6.0
7.5
5.5
7.0
5.0
6.5
5.0
7.5
6.0
5.5
4.5
Units
f
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Maximum Clock
Frequency
Propagation Delay
CP to O
n
Propagation Delay
CP to O
n
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
Note 7:
Voltage Range 3.3 is 3.3V
±
0.3V
Voltage Range 5.0 is 5.0V
±
0.5V
5
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