a
FEATURES
Fast: 2.5 ns Propagation Delay
Low Power: 118 mW per Comparator
Packages: DIP, SOIC, PLCC
Power Supplies: +5 V, –5.2 V
Logic Compatibility: ECL
50 ps Delay Dispersion
APPLICATIONS
High Speed Triggers
High Speed Line Receivers
Threshold Detectors
Window Comparators
Peak Detectors
Ultrafast Comparators
AD96685/AD96687
AD96685 FUNCTIONAL BLOCK DIAGRAM
NONINVERTING
INPUT
INVERTING
INPUT
R
L
R
L
Q
OUTPUT
Q OUTPUT
LATCH
ENABLE
V
T
AD96687 FUNCTIONAL BLOCK DIAGRAM
NONINVERTING
INPUT
Q
OUTPUT
Q OUTPUT
INVERTING
INPUT
LE
LE
V
T
R
L
R
L
Q
OUTPUT
Q OUTPUT
R
L
R
L
LE
INVERTING
INPUT
LE
NONINVERTING
INPUT
LATCH
ENABLE
LATCH
ENABLE
THE OUTPUTS ARE OPEN EMITTERS, REQUIRING EXTERNAL
PULL-DOWN RESISTORS. THESE RESISTORS MAY BE IN THE
RANGE OF 50 -200 CONNECTED TO –2.0V, OR 200 -2000
GENERAL DESCRIPTION
The AD96685 and AD96687 are ultrafast voltage comparators.
The AD96685 is a single comparator with 2.5 ns propagation
delay; the AD96687 is an equally fast dual comparator. Both
devices feature 50 ps propagation delay dispersion which is a
particularly important characteristic of high-speed comparators.
It is a measure of the difference in propagation delay under
differing overdrive conditions.
A fast, high precision differential input stage permits consistent
propagation delay with a wide variety of signals in the common-
mode range from –2.5 V to +5 V. Outputs are complementary
digital signals fully compatible with ECL 10 K and 10 KH logic
families. The outputs provide sufficient drive current to directly
drive transmission lines terminated in 50
Ω
to –2 V. A level
sensitive latch input which permits tracking, track-hold, or
sample-hold modes of operation is included.
The AD96685 is available in industrial –25°C to +85°C range
in 16-pin SOIC.
The AD96687 is available in industrial range –25°C to +85°C,
in 16-pin DIP, SOIC, and 20-lead PLCC.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD96685/AD96687–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(Positive Supply Voltage = 5.0 V; Negative Supply Voltage = –5.2 V, unless otherwise noted.)
Industrial Temperature Range –25 C to +85 C
Parameter
INPUT CHARACTERISTICS
Input Offset Voltage
Input Offset Drift
Input Bias Current
Input Offset Current
Input Resistance
Input Capacitance
Input Voltage Ranges
2
Common-Mode Rejection Ratio
ENABLE INPUT
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
DIGITAL OUTPUTS
3
Logic “1” Voltage
Logic “0” Voltage
SWITCHING PERFORMANCES
Propagation Delays
4
Input to Output HIGH
Input to Output LOW
Latch Enable to Output HIGH
Latch Enable to Output LOW
Dispersions
5
Latch Enable
Minimum Pulsewidth
Minimum Setup Time
Minimum Hold Time
POWER SUPPLY
6
Positive Supply Current (+5.0 V)
Negative Supply Current (–5.2 V)
Power Supply Rejection Ratio
7
Temp
25°C
Full
Full
25°C
Full
25°C
Full
25°C
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Test
Level
I
VI
V
I
VI
I
VI
V
V
VI
VI
VI
VI
VI
VI
VI
VI
Min
AD96685BR
Typ
Max
1
20
7
0.1
200
2
–2.5
80
–1.1
–1.5
40
5
–1.1
–1.5
–1.1
–1.5
+5.0
90
–2.5
80
–1.1
–1.5
40
5
2
3
10
13
1.0
1.2
AD96687BQ/BP/BR
Min
Typ
Max
1
20
7
0.1
200
2
+5.0
90
2
3
10
13
1.0
1.2
Unit
mV
mV
µV/°C
µA
µA
µA
µA
kΩ
pF
V
dB
V
V
µA
µA
V
V
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
Full
IV
IV
IV
IV
V
IV
IV
IV
VI
VI
VI
2.5
2.5
2.5
2.5
50
2.0
0.5
0.5
8
15
70
3.5
3.5
3.5
3.5
3.0
1.0
1.0
9
18
60
2.5
2.5
2.5
2.5
50
2.0
0.5
0.5
15
31
70
3.5
3.5
3.5
3.5
3.0
1.0
1.0
18
36
ns
ns
ns
ns
ps
ns
ns
ns
mA
mA
dB
60
NOTES
1
R
S
= 100
Ω.
2
Input Voltage Range can be extended to –3.3 V if –V
S
= –6.0 V.
3
Outputs terminated through 50
Ω
to –2.0 V.
4
Propagation delays measured with 100 mV pulse (10 mV overdrive) to 50% transition point of the output.
5
Change in propagation delay from 100 mV to 1 V input overdrive.
6
Supply voltages should remain stable within
±
5% for normal operation.
7
Measured at
±
5% of +V
S
and –V
S
.
Specifications subject to change without notice.
LATCH
ENABLE
COMPARE
LATCH
50%
t
S
t
H
V
DD
V
IN
t
S
t
H
t
PD
– Minimum Setup Time
– Minimum Hold Time
– Input to Output Delay
DIFFERENTIAL
INPUT
VOLTAGE
t
PW
(E)
V
OS
Q
t
PD
t
PD
(E)
50%
t
PD
(E) – LATCH ENABLE to Output Delay
t
PW
(E) – Minimum LATCH ENABLE Pulsewidth
V
OS
– Input Offset Voltage
– Overdrive Voltage
Q
50%
V
OD
Figure 1. System Timing Diagram
–2–
REV. D
AD96685/AD96687
ABSOLUTE MAXIMUM RATINGS
1
EXPLANATION OF TEST LEVELS
Positive Supply Voltage (+V
S
) . . . . . . . . . . . . . . . . . . . . . 6.5 V
Negative Supply Voltage (–V
S
) . . . . . . . . . . . . . . . . . . . –6.5 V
Input Voltage Range
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
5 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Latch Enable Voltage . . . . . . . . . . . . . . . . . . . . . . . . –V
S
to 0 V
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Operating Temperature Range
3
AD96685BR/AD96687BQ/BR/BP . . . . . . . –25°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –55°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 175°C
Lead Soldering Temperature (10 sec) . . . . . . . . . . . . . . 300°C
NOTES
1
Absolute maximum ratings are limiting values, may be applied individually, and
beyond which serviceability of the circuit may be impaired. Functional operation
under any of these conditions is not necessarily implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
Under no circumstances should the input voltages exceed the supply voltages.
3
Typical thermal impedances . . .
AD96685 SOIC
q
JA
= 170°C/W; q
JC
= 60°C/W
AD96687 Ceramic
q
JA
= 115°C/W; q
JC
= 57°C/W
AD96687 SOIC
q
JA
= 92°C/W; q
JC
= 47°C/W
AD96687 PLCC
q
JA
= 81°C/W; q
JC
= 45°C/W
Test Level
I – 100% production tested.
II – 100% production tested at 25°C, and sample tested at
specified temperatures.
III – Sample tested only.
IV – Parameter is guaranteed by design and characterization
testing.
V – Parameter is a typical value only.
VI – All devices are 100% production tested at 25°C; 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature ex-
tremes for commercial/industrial devices.
FUNCTIONAL DESCRIPTION
Pin Name
+V
S
NONINVERTING INPUT
INVERTING INPUT
LATCH ENABLE
Description
Positive supply terminal, nominally 5.0 V.
Noninverting analog input of the differential input stage. The NONINVERTING INPUT must be
driven in conjunction with the INVERTING INPUT.
Inverting analog input of the differential input stage. The INVERTING INPUT must be driven in
conjunction with the NONINVERTING INPUT.
In the “compare” mode (logic HIGH), the output will track changes at the input of the compara-
tor. In the “latch” mode (logic LOW), the output will reflect the input state just prior to the
comparator being placed in the “latch” mode.
LATCH ENABLE
must be driven in conjunction
with LATCH ENABLE for the AD96687.
In the “compare” mode (logic LOW), the output will track changes at the input of the comparator.
In the “latch” mode (logic HIGH), the output will reflect the input state just prior to the comparator
being placed in the “latch” mode. LATCH ENABLE must be driven in conjunction with
LATCH ENABLE
for the AD96687.
Negative supply terminal, nominally –5.2 V.
One of two complementary outputs. Q will be at logic HIGH if the analog voltage at the
NONINVERTING INPUT is greater than the analog voltage at the INVERTING INPUT (pro-
vided the comparator is in the “compare” mode). See LATCH ENABLE and LATCH ENABLE
(AD96687 only) for additional information.
One of two complementary outputs.
Q
will be at logic LOW if the analog voltage at the
NONINVERTING INPUT is greater than the analog voltage at the INVERTING INPUT
(provided the comparator is in the “compare” mode). See LATCH ENABLE and LATCH ENABLE
(AD96687 only) for additional information.
One of two grounds, but primarily associated with the digital ground. Both grounds should be
connected together near the comparator.
One of two grounds, but primarily associated with the analog ground. Both grounds should be
connected together near the comparator.
LATCH ENABLE
–V
S
Q
Q
GROUND 1
GROUND 2
REV. D
–3–
AD96685/AD96687
PIN CONFIGURATIONS
AD96685BR
GROUND 1
1
V
S
+
NONINVERTING
INPUT
INVERTING
INPUT
NC
2
3
4
16
GROUND 2
15
NC
14
NC
AD96687BP
Q OUTPUT
Q OUTPUT
Q
OUTPUT
Q
OUTPUT
AD96687BQ/BR
Q OUTPUT
1
Q
OUTPUT
2
GROUND
3
18
GROUND
17
16
Q OUTPUT
15
Q
OUTPUT
14
GROUND
3
2
NC
1
20
19
13
NC
TOP VIEW
5
(Not to Scale)
12
Q
OUTPUT
11
Q OUTPUT
10
NC
9
AD96685
LATCH ENABLE
6
NC
7
V
S
–
8
NC
GROUND
LATCH
ENABLE
NC
LATCH
ENABLE
V
S
–
4
5
6
7
8
9
10
11
12
13
AD96687
TOP VIEW
(Not to Scale)
16
15
14
LATCH
ENABLE
NC
LATCH
ENABLE
V
S
+
13
LATCH ENABLE
TOP VIEW
LATCH ENABLE
5
(Not to Scale)
12
LATCH ENABLE
LATCH ENABLE
4
AD96687
V
S
–
6
INVERTING INPUT
7
NONINVERTING
8
INPUT
11
V
S
+
10
INVERTING INPUT
9
NONINVERTING
INPUT
NC = NO CONNECT
NC = NO CONNECT
ORDERING GUIDE
Model
AD96685BR
AD96687BP
AD96687BQ
AD96687BR
AD96687BR-REEL
Type
Single
Dual
Dual
Dual
Dual
Temperature
Range
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
INVERTING
INPUT
NONINVERTING
INPUT
NC
NONINVERTING
INPUT
INVERTING
INPUT
Description
16-Pin SOIC, Industrial
20-Pin PLCC, Industrial
16-Pin DIP, Industrial
16-Pin SOIC, Industrial
16-Pin SOIC, Industrial
Package
Options
R-16A
P-20A
Q-16
R-16A
R-16A
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD96685/AD96687 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. D
Typical Performance Characteristics–AD96685/AD96687
APPLICATIONS INFORMATION
The AD96685/AD96687 comparators are very high speed devices.
Consequently, high speed design techniques must be employed
to achieve the best performance. The most critical aspect of any
AD96685/AD96687 design is the use of a low impedance
ground plane.
Another area of particular importance is power supply decoupling.
Normally, both power supply connections should be separately
decoupled to ground through 0.1
µF
ceramic and 0.001
µF
mica
capacitors. The basic design of comparator circuits makes the
negative supply somewhat more sensitive to variations. As a
result, more attention should be placed on ensuring a “clean”
negative supply.
The LATCH ENABLE input is active LOW (latched). If the
latching function is not used, the LATCH ENABLE input should
be grounded (ground is an ECL logic HIGH). The
LATCH
ENABLE
input of the AD96687 should be tied to –2.0 V or left
“floating,” to disable the latching function. An alternate use of
the LATCH ENABLE input is as a hysteresis control input. By
varying the voltage at the LATCH ENABLE input for the
AD96685 and the differential voltage between both latch
inputs for the AD96687, small variations in the hysteresis can
be achieved.
Occasionally, one of the two comparator stages within the
AD96687 will not be used. The inputs of the unused comparator
should not be allowed to “float.” The high internal gain may
cause the output to oscillate (possibly affecting the other com-
parator which is being used) unless the output is forced into a
fixed state. This is easily accomplished by ensuring that the two
inputs are at least one diode drop apart, while also grounding
the LATCH ENABLE input.
The best performance will be achieved with the use of proper
ECL terminations. The open-emitter outputs of the AD96685/
AD96687 are designed to be terminated through 50
Ω
resis-
tors to –2.0 V, or any other equivalent ECL termination. If high
speed ECL signals must be routed more than a few centimeters,
MicroStrip or StripLine techniques may be required to ensure
proper transition times and prevent output ringing.
The AD96685/AD96687 have been specifically designed to
reduce propagation delay dispersion over an input overdrive
range of 100 mV to 1 V. Propagation delay dispersion is the
change in propagation delay which results from a change in
the degree of overdrive (how far the switching point is exceeded
by the input). The overall result is a higher degree of timing
accuracy since the AD96685/AD96687 are far less sensitive
to input variations than most comparator designs.
REV. D
–5–
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