INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4017
Johnson decade counter with 10
decoded outputs
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
FEATURES
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4017 are high-speed Si-gate CMOS
devices and are pin compatible with the “4017” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4017 are 5-stage Johnson decade
counters with 10 decoded active HIGH outputs (Q
0
to Q
9
),
an active LOW output from the most significant flip-flop
(Q
5-9
), active HIGH and active LOW clock inputs (CP
0
and
74HC/HCT4017
CP
1
) and an overriding asynchronous master reset input
(MR).
The counter is advanced by either a LOW-to-HIGH
transition at CP
0
while CP
1
is LOW or a HIGH-to-LOW
transition at CP
1
while CP
0
is HIGH (see also function
table).
When cascading counters, the Q
5-9
output, which is LOW
while the counter is in states 5, 6, 7, 8 and 9, can be used
to drive the CP
0
input of the next counter.
A HIGH on MR resets the counter to zero
(Q
0
= Q
5-9
= HIGH; Q
1
to Q
9
= LOW) independent of the
clock inputs (CP
0
and CP
1
).
Automatic code correction of the counter is provided by an
internal circuit: following any illegal code the counter
returns to a proper counting mode within 11 clock pulses.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL
/ t
PLH
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+∑ (C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
PARAMETER
propagation delay CP
0
, CP
1
to Q
n
maximum clock frequency
input capacitance
power dissipation capacitance per package
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V 20
77
3.5
35
HCT
21
67
3.5
36
ns
MHz
pF
pF
UNIT
December 1990
2
Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
PIN DESCRIPTION
PIN NO.
3, 2, 4, 7, 10, 1, 5, 6, 9, 11
8
12
13
14
15
16
SYMBOL
Q
0
to Q
9
GND
Q
5-9
CP
1
CP
0
MR
V
CC
NAME AND FUNCTION
decoded outputs
ground (0 V)
carry output (active LOW)
74HC/HCT4017
clock input (HIGH-to-LOW, edge-triggered)
clock input (LOW-to-HIGH, edge-triggered)
master reset input (active HIGH)
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
74HC/HCT4017
Fig.4 Functional diagram.
FUNCTION TABLE
MR
H
L
L
L
L
L
L
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑
= LOW-to-HIGH clock transition
↓
= HIGH-to-LOW clock transition
CP
0
X
H
↑
L
X
H
↓
CP
1
X
↓
L
X
H
↑
L
OPERATION
Q
0
= Q
5-9
= H; Q
1
to Q
9
= L
counter advances
counter advances
no change
no change
no change
no change
December 1990
4
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