IDT74LVC138A
3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS
3-LINE TO 8-LINE
DECODER/DEMULTIPLEXER
WITH 5 VOLT TOLERANT I/O
• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 3.3V ± 0.3V, Normal Range
• V
CC
= 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
µ
• Rail-to-Rail output swing for increased noise margin
• All inputs, outputs, and I/Os are 5V tolerant
• Supports hot insertion
• Available in QSOP, SOIC, SSOP, and TSSOP packages
IDT74LVC138A
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
APPLICATIONS:
• High Output Drivers: ±24mA
• Reduced system switching noise
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
The LVC138A 3-line to 8-line decoder/demultiplexer is built using
advanced dual metal CMOS technology. This device is designed for high-
performance memory-decoding or data-routing applications requiring very
short propagation delay times. In high performance memory systems, this
decoder minimizes the effects of system decoding. When employed with
high-speed memories utilizing a fast enable circuit, the delay times of these
decoders and the enable time of the memory are usually less than the typical
access time of the memory. This means that the effective system delay
introduced by the decoder is negligible.
The conditions at the binary-select inputs and the three enable inputs
select one of eight output lines. Two active-low enable inputs and one active-
high enable input reduce the need for external gates or inverters when
expanding. A 24-line decoder can be implemented without external invert-
ers and a 32-line decoder requires only one inverter. An enable input can
be used as a data input for demultiplexing applications.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVC138A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
FUNCTIONAL BLOCK DIAGRAM
15
Y0
A
Select
Inputs
B
3
1
14
Y1
2
13
Y2
12
C
11
Y3
Y4
10
Data
Outputs
Y5
9
G1
Enable
Inputs
6
7
Y6
Y7
4
G2A
G2B
5
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
©1999 Integrated Device Technology, Inc.
AUGUST 1999
DSC-4722/1
IDT74LVC138A
3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
A
B
C
G2A
G2B
G
1
Y
7
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Description
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
O
< 0
Continuous Current through each
V
CC
or GND
Max
–0.5 to +6.5
–65 to +150
–50 to +50
–50
±100
Unit
V
°C
mA
mA
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
QSOP/ SOIC/ SSOP/ TSSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
G1
G2A, G2B
Yx
A, B, C
Input Enable
Input Enables (Active LOW)
Data Outputs
Select Data Inputs
Description
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output Capacitance
I/O Port Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
4.5
5.5
6.5
Max.
6
8
8
Unit
pF
pF
pF
NOTE:
1. As applicable to the device type.
FUNCTION TABLE
(1)
Enable Inputs
G1
X
X
L
H
H
H
H
H
H
H
H
G2A
H
X
X
L
L
L
L
L
L
L
L
G2B
X
H
X
L
L
L
L
L
L
L
L
C
X
X
X
L
L
L
L
H
H
H
H
Select Inputs
B
X
X
X
L
L
H
H
L
L
H
H
A
X
X
X
L
H
L
H
L
H
L
H
Y0
H
H
H
L
H
H
H
H
H
H
H
Y1
H
H
H
H
L
H
H
H
H
H
H
Y2
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
Outputs
Y3
Y4
H
H
H
H
H
H
H
L
H
H
H
Y5
H
H
H
H
H
H
H
H
L
H
H
Y6
H
H
H
H
H
H
H
H
H
L
H
Y7
H
H
H
H
H
H
H
H
H
H
L
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
2
IDT74LVC138A
3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= –40°C to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
OFF
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
High Impedance Output Current
(3-State Output pins)
Input/Output Power Off Leakage
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 0V, V
IN
or V
O
≤
5.5V
V
CC
= 2.3V, I
IN
= –18mA
V
CC
= 3.3V
V
CC
= 3.6V, V
IN
= GND or V
CC
—
—
—
—
—
–0.7
100
—
±50
–1.2
—
10
µA
V
mV
µA
V
CC
= 3.6V
V
O
= 0 to 5.5V
—
—
±10
µA
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input Leakage Current
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
I
= 0 to 5.5V
Test Conditions
Min.
1.7
2
—
—
—
Typ.
(1)
—
—
—
—
—
Max.
—
—
0.7
0.8
±5
µA
V
Unit
V
Quiescent Power Supply Current
Variation
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
—
—
500
µA
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
V
CC
= 3V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
I
OL
= 12mA
I
OL
= 24mA
Test Conditions
(1)
V
CC
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
2.2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
V
Unit
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= – 40°C to + 85°C.
3
IDT74LVC138A
3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, T
A
= 25°C
V
CC
= 2.5V±0.2V
Symbol
C
PD
Parameter
Power Dissipation Capacitance
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
—
V
CC
= 3.3V±0.3V
Typical
27
Unit
pF
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.5V ± 0.2V
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
SU
t
H
t
SK
(o)
Parameter
Propagation Delay
A to B, C to Yx
Propagation Delay
G2A
or
G2B
to Yx
Propagation Delay
G1 to Yx
Setup Time, at A, B, and C before G
Hold Time, at A, B, and C after G
Output Skew
(2)
Min.
—
—
—
2.4
1.6
—
Max.
—
—
—
—
—
—
V
CC
= 2.7V
Min.
—
—
—
2.5
1.5
—
Max.
7.9
7.4
6.4
—
—
—
V
CC
= 3.3V ± 0.3V
Min.
1
1
1
2.3
1.5
—
Max.
6.7
6.5
5.8
—
—
1
Unit
ns
ns
ns
ns
ns
ns
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= – 40°C to + 85°C.
2 Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVC138A
3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC(1)
= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
V
CC(2)
= 3.3V±0.3V & 2.7V
6
2.7
1.5
300
300
50
Unit
V
V
V
mV
mV
pF
SAME PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PHL
t
PHL
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
Propagation Delay
LVC QUAD Link
V
CC
500Ω
Pulse
Generator
(1, 2)
V
LOAD
Open
GND
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
SWITCH
NORMALLY
CLOSED
LOW
t
PZH
OUTPUT
SWITCH
NORMALLY
OPEN
HIGH
V
LOAD/2
V
T
t
PHZ
V
T
0V
t
PLZ
DISABLE
V
IH
V
T
0V
V
LOAD/2
V
LZ
V
OL
V
OH
V
HZ
0V
LVC QUAD Link
V
IN
D.U.T.
R
T
V
OUT
500Ω
C
L
LVC QUAD Link
Test Circuit for All Outputs
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2ns; t
R
≤
2ns.
2. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Switch
V
LOAD
GND
Open
DATA
INPUT
TIMING
INPUT
SYNCHRONOUS
CONTROL
ASYNCHRONOUS
CONTROL
t
SU
t
H
t
REM
INPUT
t
PLH1
t
PHL1
V
IH
V
T
0V
V
OH
V
T
V
OL
V
OH
V
T
V
OL
t
SU
t
H
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
LVC QUAD Link
Set-up, Hold, and Release Times
LOW-HIGH-LOW
PULSE
t
W
HIGH-LOW-HIGH
PULSE
V
T
LVC QUAD Link
OUTPUT 1
t
SK
(x)
t
SK
(x)
V
T
OUTPUT 2
t
PLH2
t
PHL2
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
LVC QUAD Link
Output Skew - t
SK
(
X
)
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
Pulse Width
5
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