Agilent HFCT-5905E MT-RJ Duplex
Single Mode Transceiver
Data Sheet
Description
The HFCT-5905E transceiver is a
high performance, cost effective
module for serial optical data
communications applications
specified for a signal rate of
155 MBd. It is designed to provide
a SONET/SDH compliant link for
155 Mb/s intermediate reach links.
The HFCT-5905 does not include a
nose shield and is not
recommended due to the potential
degradation of EMI performance in
a complete system. The HFCT-5905
is available on the rare occasion
that a system mechanical design
may not allow for a nose shield.
This module is designed for single
mode fiber and operates at a
nominal wavelength of 1300 nm.
It incorporates Agilent’s high
performance, reliable, long
wavelength optical devices and
proven circuit technology to give
long life and consistent service.
The transmitter section uses an
advanced SMQW Fabry Perot
laser with full IEC 825 and CDRH
Class I eye safety.
The receiver section uses a
MOVPE grown planar PIN
photodetector for low dark
current and excellent
responsivity.
A pseudo-ECL logic interface
simplifies interface to external
circuitry.
Features
• MT-RJ duplex single mode
transceiver
• Intermediate SONET OC3 SDH
STM1 (S1.1) compliant
• Single +3.3 V power supply
• Multisourced 2 x 5 pin
configuration
• Interchangeable with LED
multisourced 2 x 5 transceivers
• Unconditionally eye safe
laser IEC 825/CDRH Class 1
compliant
• Temperature range:
0°C to +70°C
Applications
• SONET/SDH equipment
interconnect
• ATM 155 Mb/s links
Connection Diagram
RX
TX
Mounting Studs/
Solder Posts
Package
Grounding Tabs
Top
View
RECEIVER SIGNAL GROUND
RECEIVER POWER SUPPLY
SIGNAL DETECT
RECEIVER DATA OUT BAR
RECEIVER DATA OUT
f
f
f
f
f
1
2
3
4
5
10
9
8
7
6
f
f
f
f
f
TRANSMITTER DATA IN BAR
TRANSMITTER DATA IN
TRANSMITTER DISABLE
TRANSMITTER SIGNAL GROUND
TRANSMITTER POWER SUPPLY
Pin Descriptions:
Pin 1 Receiver Signal Ground
V
EE
RX:
1
Directly connect this pin to the
receiver ground plane.
Pin 2 Receiver Power Supply
V
CC
RX:
Provide +3.3 V dc via the
recommended receiver power
supply filter circuit. Locate the
power supply filter circuit as
close as possible to the V
CC
RX
pin.
Pin 3 Signal Detect SD:
Normal optical input levels to the
receiver result in a logic “1”
output.
Low optical input levels to the
receiver result in a fault condition
indicated by a logic “0” output.
This Signal Detect output can be
used to drive a PECL input on an
upstream circuit, such as Signal
Detect input or Loss of Signal-bar.
Pin 4 Receiver Data Out Bar RD-:
No internal terminations are
provided. See recommended
circuit schematic.
Pin 5 Receiver Data Out RD+:
No internal terminations are
provided. See recommended
circuit schematic.
Pin 6 Transmitter Power Supply
V
CC
TX:
Provide +3.3 V dc via the
recommended transmitter power
supply filter circuit. Locate the
power supply filter circuit as
close as possible to the V
CC
TX
pin.
Pin 7 Transmitter Signal Ground
V
EE
TX:
Directly connect this pin to the
transmitter ground plane.
Pin 8 Transmitter Disable T
DIS
:
Optional feature for laser based
products only. For laser based
products connect this pin to
+3.3 V TTL logic high “1” to
disable module. To enable module
connect to TTL logic low “0”.
Pin 9 Transmitter Data In TD+:
No internal terminations are
provided. See recommended
circuit schematic.
Pin 10 Transmitter Data In Bar TD-:
No internal terminations are
provided. See recommended
circuit schematic.
Mounting Studs/Solder Posts
The two mounting studs are
provided for transceiver
mechanical attachment to the
circuit board. It is recommended
that the holes in the circuit board
be connected to chassis ground.
Package Grounding Tabs
Connect four package grounding
tabs to signal ground.
Note:
1. The Transmitter and Receiver V
EE
connections are commoned within the module.
2
Functional Description
Receiver Section
Design
The receiver section contains an
InGaAs/InP photo detector and a
preamplifier mounted in an
optical subassembly. This optical
subassembly is coupled to a
postamp/decision circuit on a
separate circuit board.
The postamplifier is ac coupled to
the preamplifier as illustrated in
Figure 1. The coupling capacitors
are large enough to pass the
SONET/SDH test pattern at
155 MBd without significant
distortion or performance penalty.
If a lower signal rate, or a code
which has significantly more low
frequency content is used,
sensitivity, jitter and pulse
distortion could be degraded.
Figure 1 also shows a filter
network which limits the
bandwidth of the preamp output
signal. The filter is designed to
bandlimit the preamp output
noise and thus improve the
receiver sensitivity.
These components will also
reduce the sensitivity of the
receiver as the signal bit rate is
increased above 155 MBd.
Noise Immunity
The receiver includes internal
circuit components to filter
power supply noise. Under some
conditions of EMI and power
supply noise, external power
supply filtering may be necessary.
If receiver sensitivity is found to
be degraded by power supply
noise, the filter network
illustrated in Figure 3 may be
used to improve performance.
The values of the filter
components are general
recommendations and may be
changed to suit a particular
system environment. Shielded
inductors are recommended.
Terminating the Outputs
The PECL Data outputs of the
receiver may be terminated with
the standard Thevenin-equivalent
50 ohm to V
CC
- 2 V termination.
Other standard PECL terminating
techniques may be used.
The two outputs of the receiver
should be terminated with
identical load circuits to avoid
unnecessarily large ac current in
V
CC
. If the outputs are loaded
identically the ac current is
largely nulled. The SD output of
the receiver is PECL logic and
must be loaded if it is to be used.
The signal detect circuit is much
slower that the data path, so the
ac noise generated by an
asymmetrical load is negligible.
Power consumption may be
reduced by using a higher than
normal load impedance for the SD
output. Transmission line effects
are not generally a problem as the
switching rate is slow.
The Signal Detect Circuit
The signal detect circuit works by
sensing the peak level of the
received signal and comparing
this level to a reference.
TRANS-
IMPEDANCE
PRE-
AMPLIFIER
FILTER
AMPLIFIER
PECL
OUTPUT
BUFFER
DATA OUT
DATA OUT
GND
SIGNAL
DETECT
CIRCUIT
PECL
OUTPUT
BUFFER
SD
Figure 1. Receiver Block Diagram
3
Functional Description
Transmitter Section
Design
The transmitter section uses a
buried heterostructure Fabry
Perot laser as its optical source.
The package of this laser is
designed to allow repeatable
coupling into single mode fiber.
In addition, this package has been
designed to be compliant with
IEC 825 Class 1 and CDRH Class I
eye safety requirements. The
optical output is controlled by a
custom IC which detects the laser
output via the monitor photodiode.
This IC provides both dc and ac
current drive to the laser to
ensure correct modulation, eye
diagram and extinction ratio over
temperature, supply voltage and
life.
Solder and Wash Process
Compatibility
The transceivers are delivered
with protective process plugs
inserted into the MT-RJ connector
receptacle. This process plug
protects the optical subassemblies
during wave solder and aqueous
wash processing and acts as a
dust cover during shipping.
These transceivers are compatible
with either industry standard
wave or hand solder processes.
Each process plug can only be
used once during processing,
although with subsequent use, it
can be used as a dust cover.
LASER
PHOTODIODE
(rear facet monitor)
DATA
DATA
PECL
INPUT
LASER
MODULATOR
LASER BIAS
DRIVER
LASER BIAS
CONTROL
Figure 2. Simplified Transmitter Schematic
4
Interface and Termination
Recommendations
Figure 3 shows a +3.3 V coupling
scheme. Also present are power
supply filtering arrangements
which comply with the
recommendations of the small
form factor multisource
agreement. Such a compliance
ensures noise rejection
compatibility between
transceivers from various
vendors.
PHY DEVICE
V
CC
(+3.3 V)
TERMINATE AT
TRANSCEIVER INPUTS
Z = 50
W
W
130
TD-
100
W
6
f
f
Z = 50
LVPECL
TD+
10
f
9
TD+
8
f
7
f
W
130
W
V
CC
(+3.3 V)
1 µH
C2
V
CC
(+3.3 V)
C3
10 µF
N/C
V
EE
T
X
RD-
T
X
V
EE
R
X
SD
R
X
V
CC
R
X
RD+
V
CC
T
X
TD-
1 µH
RD+
C1
Z = 50
f
f
f
f
f
1
2
3
4
5
W
W
W
100
W
RD-
LVPECL
Z = 50
V
CC
(+3.3 V)
130
W
130
W
Z = 50
130
W
SD
82
W
Note: C1 = C2 = C3 = 10 nF or 100 nF
TERMINATE AT
DEVICE INPUTS
Figure 3. +3.3 V Transceiver Interface with +3.3 V LVPECL Device
5
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