Monolithic Common Drain N-Channel 2.5V Specified PowerTrench
MOSFET
General Description
This dual N-Channel MOSFET has been designed
using Fairchild Semiconductor’s advanced Power
Trench process to optimize the R
DS(ON)
@ V
GS
= 2.5v on
special MicroFET lead frame with all the drains on one
side of the package.
Features
•
8.7 A, 20 V
R
DS(ON)
= 18 mΩ @ V
GS
= 4.5 V
R
DS(ON)
= 24 mΩ @ V
GS
= 2.5 V
•
ESD protection diode (note 3)
•
Low Profile – 0.8mm maximum – in the new package
MicroFET 2x5 mm
PIN 1
S1 S1 G1
G2
S2
S2
Bottom Drain Contact
Q2
Applications
•
Li-Ion Battery Pack
4
5
6
3
G1
2
S1
1
S1
S2 S2 G2
Q1
Bottom Drain Contact
MLP 2x5
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
T
J
, T
STG
T
A
=25 C unless otherwise noted
o
Parameter
Drain-Source Voltage
Gate-Source Voltage
– Continuous
– Pulsed
Power Dissipation (Steady State)
Drain Current
(Note 1a)
Ratings
20
±12
8.7
30
2.2
0.8
–55 to +150
Units
V
V
A
W
°C
(Note 1a)
(Note 1b)
Operating and Storage Junction Temperature
Range
Thermal Characteristics
R
θJA
R
θJC
Thermal Resistance, Junction-to-Ambient
(Note 1a)
55
2
°C/W
Thermal Resistance, Junction-to-Case (Drain)
Package Marking and Ordering Information
Device Marking
2509Z
Device
FDM2509NZ
Reel Size
7’’
Tape width
12mm
Quantity
3000 units
2006
Fairchild Semiconductor Corporation
FDM2509NZ Rev C2
FDM2509NZ
Electrical Characteristics
Symbol
BV
DSS
∆BV
DSS
∆T
J
I
DSS
I
GSS
V
GS(th)
∆V
GS(th)
∆T
J
R
DS(on)
T
A
= 25°C unless otherwise noted
Parameter
Drain–Source Breakdown
Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate–Body Leakage,
(Note 2)
Test Conditions
V
GS
= 0 V,
I
D
= 250
µA
Min
20
Typ Max
Units
V
Off Characteristics
I
D
= 250
µA,
Referenced to 25°C
V
DS
= 16 V,
V
GS
=
±12
V,
V
GS
= 0 V
V
DS
= 0 V
0.6
0.9
–3
13
13.5
15.5
18
18.4
36
1200
320
f = 1.0 MHz
185
2
12
1
±10
1.5
mV/°C
µA
µA
V
mV/°C
mΩ
On Characteristics
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
I
D
= 250
µA
V
DS
= V
GS
,
I
D
= 250
µA,
Referenced to 25 C
V
GS
= 4.5 V,
I
D
= 8.7 A
I
D
= 8.5 A
V
GS
= 4.0 V,
I
D
= 8.1 A
V
GS
= 3.1 V,
I
D
= 7.6 A
V
GS
= 2.5 V,
V
GS
= 4.5 V, I
D
= 8.7 A, T
J
= 125°C
V
DS
= 5 V,
I
D
= 8.7 A
V
DS
= 10 V,
f = 1.0 MHz
V
GS
= 50mV,
V
GS
= 0 V,
18
19
21
24
25
g
FS
C
iss
C
oss
C
rss
R
G
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
(Note 2)
S
pF
pF
pF
Ω
Dynamic Characteristics
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
I
S
V
SD
t
rr
Q
rr
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
V
DD
= 10 V,
V
GS
= 4.5 V,
I
D
= 1 A,
R
GEN
= 6
Ω
11
15
27
12
20
27
43
22
17
ns
ns
ns
ns
nC
nC
nC
V
DS
= 10 V,
V
GS
= 4.5 V
I
D
= 8.7 A,
12
2
4
Drain–Source Diode Characteristics and Maximum Ratings
Maximum Continuous Drain–Source Diode Forward Current
Drain–Source Diode Forward
V
GS
= 0 V, I
S
= 1.8 A
Voltage
I
F
= 8.7 A,
Diode Reverse Recovery Time
Diode Reverse Recovery Charge dI
F
/dt = 100 A/µs
(Note 2)
0.7
20
6.4
1.8
1.2
A
V
nS
nC
Notes:
1.
R
θJA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R
θJC
is guaranteed by design while R
θCA
is determined by the user's board design.
a)
55°C/W when
mounted on a 1in
2
pad
of 2 oz copper
Scale 1 : 1 on letter size
paper
b)
145°C/W when mounted on a
minimum pad of 2 oz copper
2.
Pulse Test: Pulse Width < 300µs,
Duty Cycle < 2.0%
3.
The diode connected between the
gate and the source serves only
as protection against ESD. No
gate overvoltage rating is
implied.
FDM2509NZ Rev C2
FDM2509NZ
Typical Characteristics
30
R
DS(ON)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
V
GS
= 4.5V
2.5V
3.0V
2.0V
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
25
I
D
, DRAIN CURRENT (A)
20
15
10
5
0
0
3.5V
V
GS
= 2.0V
2.5V
3.0V
3.5V
4.5V
0.25
0.5
0.75
1
1.25
1.5
0
5
10
15
20
25
30
V
DS
, DRAIN-SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
0.047
R
DS(ON)
, ON-RESISTANCE (OHM)
1.6
R
DS(ON)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
I
D
= 8.7A
V
GS
= 4.5V
1.4
I
D
= 4.4A
0.042
0.037
0.032
T
A
= 125
o
C
1.2
1
0.027
0.022
0.017
0.012
1
2
3
4
5
V
GS
, GATE TO SOURCE VOLTAGE (V)
0.8
T
A
= 25
o
C
0.6
-50
-25
0
25
50
75
100
o
125
150
T
J
, JUNCTION TEMPERATURE ( C)
Figure 3. On-Resistance Variation with
Temperature.
30
25
I
D
, DRAIN CURRENT (A)
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
100
25
o
C
125
o
C
I
S
, REVERSE DRAIN CURRENT (A)
V
DS
= 5V
T
A
= -55
o
C
10
1
V
GS
= 0V
20
15
10
5
0
0.5
1
1.5
2
2.5
V
GS
, GATE TO SOURCE VOLTAGE (V)
T
A
= 125
o
C
0.1
0.01
0.001
0.0001
0
0.2
0.4
0.6
0.8
1
1.2
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
25
o
C
-55
o
C
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
FDM2509NZ Rev C2
FDM2509NZ
Typical Characteristics
5
V
GS
, GATE-SOURCE VOLTAGE (V)
1800
I
D
= 8.7A
4
V
DS
= 5V
CAPACITANCE (pF)
1600
f = 1MHz
V
GS
= 0 V
C
iss
10V
15V
1400
1200
1000
800
600
400
200
3
2
C
oss
1
C
rss
0
4
8
12
16
20
0
0
3
6
9
12
15
Q
g
, GATE CHARGE (nC)
0
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics.
100
P(pk), PEAK TRANSIENT POWER (W)
Figure 8. Capacitance Characteristics.
50
R
DS(ON)
LIMIT
I
D
, DRAIN CURRENT (A)
100us
1ms
10ms
100ms
1s
10s
DC
10
40
SINGLE PULSE
R
θ
JA
= 145°C/W
T
A
= 25°C
30
1
V
GS
= 4.5V
SINGLE PULSE
R
θ
JA
= 145
o
C/W
T
A
= 25 C
0.01
0.1
1
o
20
0.1
10
10
100
0
0.001
0.01
0.1
1
t
1
, TIME (sec)
10
100
1000
V
DS
, DRAIN-SOURCE VOLTAGE (V)
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum
Power Dissipation.
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
1
D = 0.5
R
θJA
(t) = r(t) * R
θJA
R
θJA
=145 °C/W
P(pk)
t
1
t
2
T
J
- T
A
= P * R
θJA
(t)
Duty Cycle, D = t
1
/ t
2
SINGLE PULSE
0.2
0.1
0.1
0.05
0.02
0.01
0.01
0.0001
0.001
0.01
0.1
t
1
, TIME (sec)
1
10
100
1000
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1b.
Transient thermal response will change depending on the circuit board design.
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