HIGH-SPEED 2.5V
512/256/128K X 18
IDT70T3339/19/99S
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
◆
◆
◆
◆
◆
◆
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz)(max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Interrupt and Collision Detection Flags
Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– Data input, address, byte enable and control registers
◆
◆
◆
◆
◆
◆
◆
◆
– 1.5ns setup to clock and 0.5ns hold on all control, data,
and address inputs @ 200MHz
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
2.5V (±100mV) power supply for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
Available in a 256-pin Ball Grid Array (BGA) and 208-pin fine
pitch Ball Grid Array (fpBGA)
Supports JTAG features compliant with IEEE 1149.1
Green parts available, see ordering information
Functional Block Diagram
UB
L
LB
L
UB
R
LB
R
FT/PIPE
L
1/0
0a 1a
a
0b 1b
b
1b 0b
b
1a 0a
a
1/0
FT/PIPE
R
R/W
L
CE
0L
CE
1L
1
0
1/0
B B
WW
0 1
L L
B B
WW
1 0
R R
1
0
1/0
R/W
R
CE
0R
CE
1R
OE
L
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
OE
R
1b 0b 1a 0a
FT/PIPE
L
0/1
0a 1a 0b
1b
,
0/1
FT/PIPE
R
ab
512/256/128K x 18
MEMORY
ARRAY
ba
I/O
0L
- I/O
17L
Din_L
Din_R
I/O
0R
- I/O
17R
CLK
L
A
18L
(1)
A
0L
REPEAT
L
ADS
L
CNTEN
L
A
18R (1)
CLK
R
,
Counter/
Address
Reg.
ADDR_L
ADDR_R
Counter/
Address
Reg.
A
0R
REPEAT
R
ADS
R
CNTEN
R
TDI
TCK
TMS
TRST
CE
0 L
CE1L
R/
W
L
INTERRUPT
COLLISION
DETECTION
LOGIC
CE
0 R
CE1R
R/
W
R
JTAG
TDO
COL
L
INT
L
ZZ
L
(2)
COL
R
INT
R
ZZ
CONTROL
LOGIC
ZZ
R
(2)
5652 drw 01
NOTES:
1. Address A
18
is a NC for the IDT70T3319. Also, Addresses A
18
and A
17
are NC's for the IDT70T3399.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and
OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
APRIL 2010
DSC-5652/7
1
©2010 Integrated Device Technology, Inc.
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT70T3339/19/99 is a high-speed 512/256/128k x 18 bit
synchronous Dual-Port RAM. The memory array utilizes Dual-Port
memory cells to allow simultaneous access of any address from both ports.
Registers on control, data, and address inputs provide minimal setup and
hold times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times. With an input data register, the
IDT70T3339/19/99 has been optimized for applications having unidirec-
tional or bidirectional data flow in bursts. An automatic power down feature,
controlled by
CE
0
and CE
1,
permits the on-chip circuitry of each port to
enter a very low standby power mode.
The IDT70T3339/19/99 can support an operating voltage of either
3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power
supply for the core of the device (V
DD
) is at 2.5V.
6.42
2
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration
(3,4,5,6,9)
70T3339/19/99BC
BC-256
(8)
01/13/03
A1
A2
A3
A4
A5
A6
A7
256-Pin BGA
Top View
(9)
A8
A9
A10
A11
A12
A13
A14
A15
A16
NC
B1
TDI
B2
NC
B3
A
17L
(2)
A
14L
B4
B5
A
11L
B6
A
8L
B7
NC
B8
CE
1L
B9
OE
L
CNTEN
L
A
5L
B10
B11
B12
A
2L
B13
A
0L
B14
NC
B15
NC
B16
INT
L
C1
NC
C2
TDO A
18L
(1)
A
15L
C3
C4
C5
A
12L
C6
A
9L
C7
UB
L
C8
CE
0L
R/W
L
REPEAT
L
C9
C10
C11
A
4L
C12
A
1L
C13
V
DD
C14
NC
C15
NC
C16
COL
L
I/O
9L
D1
D2
V
SS
D3
A
16L
D4
A
13L
D5
A
10L
D6
A
7L
D7
NC
D8
LB
L
D9
CLK
L
ADS
L
D10
D11
A
6L
D12
A
3L
D13
OPT
L
D14
NC
D15
I/O
8L
D16
NC
E1
I/O
9R
E2
NC
E3
PIPE/
FT
L
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DD
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
NC
E14
NC
E15
I/O
8R
E16
I/O
10R
I/O
10L
F1
F2
NC
F3
V
DDQL
V
DD
F4
F5
V
DD
F6
NC
F7
V
SS
F8
V
SS
F9
V
SS
F10
V
DD
F11
V
DD
V
DDQR
F12
F13
NC
F14
I/O
7L
I/O
7R
F15
F16
I/O
11L
G1
NC
G2
I/O
11R
V
DDQL
V
DD
G3
G4
G5
NC
G6
NC
G7
V
SS
G8
V
SS
G9
V
SS
G10
V
SS
G11
V
DD
V
DDQR
I/O
6R
G12
G13
G14
NC
G15
I/O
6L
G16
NC
H1
NC
H2
I/O
12L
V
DDQR
H3
H4
V
SS
H5
V
SS
H6
V
SS
H7
V
SS
H8
V
SS
H9
V
SS
H10
V
SS
H11
V
SS
H12
V
DDQL
I/O
5L
H13
H14
NC
H15
NC
H16
NC
J1
I/O
12R
J2
NC V
DDQR
V
SS
J3
J4
J5
V
SS
J6
V
SS
J7
V
SS
J8
V
SS
J9
V
SS
J10
V
SS
J11
V
SS
J12
V
DDQL
J13
NC
J14
NC
J15
I/O
5R
J16
I/O
13L
I/O
14R
I/O
13R
V
DDQL
ZZ
R
K1
K2
K3
K4
K5
V
SS
K6
V
SS
K7
V
SS
K8
V
SS
K9
V
SS
K10
V
SS
K11
ZZ
L
V
DDQR
I/O
4R
I/O
3R
I/O
4L
K12
K13
K14
K15
K16
NC
L1
NC
L2
I/O
14L
V
DDQL
V
SS
L3
L4
L5
V
SS
L6
V
SS
L7
V
SS
L8
V
SS
L9
V
SS
L10
V
SS
L11
V
SS
L12
V
DDQR
NC
L13
L14
NC
L15
I/O
3L
L16
I/O
15L
M1
NC
M2
I/O
15R
V
DDQR
V
DD
M3
M4
M5
NC
M6
NC
M7
V
SS
M8
V
SS
M9
V
SS
M10
V
SS
M11
V
DD
M12
V
DDQL
I/O
2L
M13
M14
NC
M15
I/O
2R
M16
I/O
16R
I/O
16L
N1
N2
NC V
DDQR
N3
N4
V
DD
N5
V
DD
N6
NC
N7
V
SS
N8
V
SS
N9
V
SS
N10
V
DD
N11
V
DD
N12
V
DDQL
I/O
1R
N13
N14
I/O
1L
N15
NC
N16
NC
P1
I/O
17R
P2
NC
PIPE/
FT
R
V
DDQR
V
DDQR
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DDQL
V
DDQL
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
V
DD
P13
NC
P14
I/O
0R
P15
NC
P16
COL
R
I/O
17L
TMS
R1
R2
R3
A
16R
R4
18R
(1)
A
13R
R5
A
10R
R6
A
7R
R7
NC
R8
LB
R
R9
CLK
R
ADS
R
R10
R11
A
6R
R12
A
3R
R13
NC
R14
NC
R15
I/O
0L
R16
INT
R
T1
NC
T2
TRST
A
T3
A
15R
T5
A
12R
T6
A
9R
T7
UB
R
T8
CE
0R
R/W
R
REPEAT
R
A
4R
T9
T10
T11
T12
A
1R
T13
OPT
R
T14
NC
T15
NC
T16
,
T4
NC
TCK
NC
A
17R
(2)
A
14R
A
11R
A
8R
NC
CE
1R
OE
R
CNTEN
R
A
5R
A
2R
A
0R
NC
NC
5652 drw 02d
NOTES:
1. Pin is a NC for IDT70T3319 and IDT70T3399.
2. Pin is a NC for IDT70T3399.
3. All V
DD
pins must be connected to 2.5V power supply.
4. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
DD
(2.5V), and 2.5V if OPT pin for that port is
set to V
SS
(0V).
5. All V
SS
pins must be connected to ground supply.
6. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
9. Pins A15 and T15 will be V
REFL
and V
REFR
respectively for future HSTL device.
,
6.42
3
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations(con't)
(3,4,5,6,9)
01/13/03
1
I/O
9L
2
INT
L
3
V
SS
4
TDO
5
NC
6
A
16L
7
A
12L
8
A
8L
9
NC
10 11
V
DD
CLK
L
12
CNTEN
L
13 14
A
4L
A
0L
15
OPT
L
16 17
NC
V
SS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
NC
V
SS
COL
L
TDI
A
17L(2)
A
13L
A
9L
NC
CE
0L
V
SS
ADS
L
A
5L
A
1L
NC
V
DDQR
I/O
8L
NC
V
DDQL
I/O
9R
V
DDQR
PIPE/
FT
L
A
18L(1)
A
14L
A
10L
UB
L
CE
1L
V
SS
R/W
L
A
6L
A
2L
V
DD
I/O
8R
NC
V
SS
NC
V
SS
I/O
10L
NC
A
15L
A
11L
A
7L
LB
L
V
DD
OE
L
REPEAT
L
A
3L
V
DD
NC
V
DDQL
I/O
7L
I/O
7R
I/O
11L
NC
V
DDQR
I/O
10R
I/O
6L
NC
V
SS
NC
V
DDQL
I/O
11R
NC
V
SS
V
SS
I/O
6R
NC
V
DDQR
NC
V
SS
I/O
12L
NC
NC
V
DDQL
I/O
5L
NC
V
DD
NC
V
DDQR
I/O
12R
70T3339/19/99BF
BF-208
(7)
208-Pin fpBGA
Top View
(8)
V
DD
NC
V
SS
I/O
5R
V
DDQL
V
DD
V
SS
ZZ
R
ZZ
L
V
DD
V
SS
V
DDQR
I/O
14R
V
SS
I/O
13R
V
SS
I/O
3R
V
DDQL
I/O
4R
V
SS
NC
I/O
14L
V
DDQR
I/O
13L
NC
I/O
3L
V
SS
I/O
4L
V
DDQL
NC
I/O
15R
V
SS
V
SS
NC
I/O
2R
V
DDQR
NC
V
SS
NC
I/O
15L
I/O
1R
V
DDQL
NC
I/O
2L
I/O
16R
I/O
16L
V
DDQR
COL
R
TRST
A
16R
A
12R
A
8R
NC
V
DD
CLK
R
CNTEN
R
A
4R
NC
I/O
1L
V
SS
NC
V
SS
NC
I/O
17R
TCK
A
17R(2)
A
13R
A
9R
NC
CE
0R
V
SS
ADS
R
A
5R
A
1R
NC
V
DDQL
I/O
0R
V
DDQR
NC
I/O
17L
V
DDQL
TMS
A
18R(1)
A
14R
A
10R
UB
R
CE
1R
V
SS
R/W
R
A
6R
A
2R
V
SS
NC
V
SS
NC
V
SS
INT
R
PIPE/
FT
R
NC
A
15R
A
11R
A
7R
LB
R
V
DD
OE
R
REPEAT
R
A
3R
A
0R
V
DD
OPT
R
NC
I/O
0L
5652 drw 02c
NOTES:
1. Pin is a NC for IDT70T3319 and IDT70T3399.
2. Pin is a NC for IDT70T3399.
3. All V
DD
pins must be connected to 2.5V power supply.
4. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
DD
(2.5V), and 2.5V if OPT pin for that port is
set to V
SS
(0V).
5. All V
SS
pins must be connected to ground supply.
6. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
9. Pins B14 and R14 will be V
REFL
and V
REFR
respectively for future HSTL device.
6.42
4
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
CE
0L
,
CE
1L
R/W
L
OE
L
A
0L
- A
18L
(5)
I/O
0L
- I/O
17L
CLK
L
PL/FT
L
ADS
L
CNTEN
L
REPEAT
L
UB
L
LB
L
V
DDQL
OPT
L
ZZ
L
V
DD
V
SS
TDI
TDI
TCK
TMS
TRST
INT
L
COL
L
INT
R
COL
R
Right Port
CE
0R
,
CE
1R
R/W
R
OE
R
A
0R
- A
18R
(5)
I/O
0R
- I/O
17R
CLK
R
PL/FT
R
ADS
R
CNTEN
R
REPEAT
R
UB
R
LB
R
V
DDQR
OPT
R
ZZ
R
Names
Chip Enables (Input)
(6)
Read/Write Enable (Input)
Output Enable (Input)
Address (Input)
Data Input/Output
Clock (Input)
Pipeline/Flow-Through (Input)
Address Strobe Enable (Input)
Counter Enable (Input)
Counter Repeat
(3)
Upper Byte Enable (I/O
9
- I/O
17
)
(6)
Lower Byte Enable (I/O
0
- I/O
8
)
(6)
Power (I/O Bus) (3.3V or 2.5V)
(1)
(Input)
Option for selecting V
DDQX
(1,2)
(Input)
Sleep Mode pin
(4)
(Input)
Power (2.5V)
(1)
(Input)
Ground (0V) (Input)
Test Data Input
Test Data Output
Test Logic Clock (10MHz) (Input)
Test Mode Select (Input)
Reset (Initialize TAP Controller) (Input)
Interrupt Flag (Output)
Collision Alert (Output)
5652 tbl 01
NOTES:
1. V
DD
, OPT
X
, and V
DDQX
must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPT
X
selects the operating voltage levels for the I/Os and controls on that port.
If OPT
X
is set to V
DD
(2.5V), then that port's I/Os and controls will operate at 3.3V
levels and V
DDQX
must be supplied at 3.3V. If OPT
X
is set to V
SS
(0V), then that
port's I/Os and address controls will operate at 2.5V levels and V
DDQX
must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
3. When
REPEAT
X
is asserted, the counter will reset to the last valid address loaded
via
ADS
X
.
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins
themselves (ZZx) are not affected during sleep mode. It is recommended that
boundry scan not be operated during sleep mode.
5. Address A
18x
is a NC for the IDT70T3319. Also, Addresses A
18x
and A
17x
are
NC's for the IDT70T3399.
6. Chip Enables and Byte Enables are double buffered when PL/FT = V
IH
, i.e., the
signals take two cycles to deselect.
6.42
5
电源技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
