Datasheet> 器件分类 > 逻辑> 逻辑> SY10EL38LZCTR

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SY10EL38LZCTR: 产品描述5V/3.3V ±2, ±4/6 CLOCK GENERATION CHIP; 产品类别逻辑逻辑; 文件大小97KB，共6页; 制造商Microchip(微芯科技); 官网地址https://www.microchip.com

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SY10EL38LZCTR概述

5V/3.3V ±2, ±4/6 CLOCK GENERATION CHIP

SY10EL38LZCTR规格参数

参数名称	属性值
厂商名称	Microchip(微芯科技)
包装说明	SOP,
Reach Compliance Code	compli
系列	10EL
输入调节	DIFFERENTIAL
JESD-30 代码	R-PDSO-G20
长度	12.83 mm
逻辑集成电路类型	LOW SKEW CLOCK DRIVER
功能数量	1
反相输出次数
端子数量	20
实输出次数	8
封装主体材料	PLASTIC/EPOXY
封装代码	SOP
封装形状	RECTANGULAR
封装形式	SMALL OUTLINE
传播延迟（tpd）	1.22 ns
Same Edge Skew-Max（tskwd）	0.075 ns
座面最大高度	2.65 mm
表面贴装	YES
技术	ECL
端子形式	GULL WING
端子节距	1.27 mm
端子位置	DUAL
宽度	7.52 mm
最小 fmax	1000 MHz

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NOT RECOMMENDED FOR NEW DESIGNS

Micrel, Inc.

5V/3.3V

4/6 CLOCK

GENERATION CHIP

Precision Edge

SY10EL38/L

Precision Edge

SY100EL38/L

SY10EL38/L

SY100EL38/L

FEATURES

3.3V and 5V power supply options

50ps output-to-output skew

Synchronous enable/disable

Master Reset for synchronization

Internal 75K

Ω

input pull-down resistors

Precision Edge

DESCRIPTION

The SY10/100EL38/L are low skew

÷2, ÷4/6

clock

generation chips designed explicitly for low skew clock

generation applications. The internal dividers are

synchronous to each other, therefore, the common output

edges are all precisely aligned. The devices can be driven

by either a differential or single-ended ECL or, if positive

power supplies are used, PECL input signal. In addition,

by using the V

output, a sinusoidal source can be AC-

coupled into the device. If a single-ended input is to be

used, the V

output should be connected to the CLK

input and bypassed to ground via a 0.01µF capacitor.

The V

output is designed to act as the switching

reference for the input of the EL38/L under single-ended

input conditions. As a result, this pin can only source/

sink up to 0.5mA of current.

The common enable (EN) is synchronous so that the

internal dividers will only be enabled/disabled when the

internal clock is already in the LOW state. This avoids

any chance of generating a runt clock pulse on the

internal clock when the device is enabled/disabled as

can happen with an asynchronous control. An internal

runt pulse could lead to losing synchronization between

the internal divider stages. The internal enable flip-flop is

clocked on the falling edge of the input clock, therefore,

all associated specification limits are referenced to the

negative edge of the clock input.

The Phase_Out output will go HIGH for one clock cycle

whenever the

÷2

and the

÷4/6

outputs are both

transitioning from a LOW to a HIGH. This output allows

for clock synchronization within the system.

Upon start-up, the internal flip-flops will attain a

random state; the master reset (MR) input allows for the

synchronization of the internal dividers, as well as for

multiple EL38/Ls in a system.

Available in 20-pin SOIC package

Precision Edge is a registered trademark of Micrel, Inc.

M9999-031006

hbwhelp@micrel.com or (408) 955-1690

Rev.: G

Amendment: /0

Issue Date: March 2006

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