INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT20
Dual 4-input NAND gate
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
Dual 4-input NAND gate
FEATURES
•
Output capability: standard
•
I
CC
category: SSI
GENERAL DESCRIPTION
74HC/HCT20
The 74HC/HCT20 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT20 provide the 4-input NAND function.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL
/ t
PLH
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
f
o
= input frequency in MHz
= output frequency in MHz
PARAMETER
propagation delay nA, nB, nC, nD to nY
input capacitance
power dissipation capacitance per package
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
8
3.5
22
HCT
13
3.5
17
ns
pF
pF
UNIT
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
Dual 4-input NAND gate
PIN DESCRIPTION
PIN NO.
1, 9
2, 10
3, 11
4, 12
5, 13
6, 8
7
14
SYMBOL
1A, 2A
1B, 2B
n.c.
1C, 2C
1D, 2D
1Y, 2Y
GND
V
CC
NAME AND FUNCTION
data inputs
data inputs
not connected
data inputs
data inputs
data outputs
ground (0 V)
positive supply voltage
74HC/HCT20
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Dual 4-input NAND gate
74HC/HCT20
Fig.4 Functional diagram.
Fig.5 HC logic diagram (one gate).
FUNCTION TABLE
INPUTS
nA
L
X
X
X
H
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Fig.6 HCT logic diagram (one gate).
nB
X
L
X
X
H
nC
X
X
L
X
H
nD
X
X
X
L
H
OUTPUT
nY
H
H
H
H
L
December 1990
4
Philips Semiconductors
Product specification
Dual 4-input NAND gate
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: SSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL
PARAMETER
+25
min.
t
PHL
/ t
PLH
propagation delay
nA, nB, nC, nD to nY
output transition time
typ.
28
10
8
19
7
6
max.
90
18
15
75
15
13
−40
to +85
min.
max.
115
23
20
95
19
16
−40
to +125
min.
max.
135
27
23
110
22
19
ns
UNIT
74HC/HCT20
TEST CONDITIONS
V
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
WAVEFORMS
Fig.7
t
THL
/ t
TLH
ns
Fig.7
December 1990
5
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