INTEGRATED CIRCUITS
PCA9540
2-channel I
2
C multiplexer
Product data
Supersedes data of 2001 Feb 08
2002 May 13
Philips
Semiconductors
Philips Semiconductors
Product data
2-channel I
2
C multiplexer
PCA9540
FEATURES
•
1-of-2 bi-directional translating multiplexer
•
I
2
C interface logic; compatible with SMBus standards
•
Channel selection via I
2
C bus
•
Power up with all multiplexer channels deselected
•
Low Rds
ON
switches
•
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and
5 V buses
PIN CONFIGURATION
SCL
SDA
V
DD
SD0
1
2
3
4
8
7
6
5
SC1
SD1
V
SS
SC0
•
No glitch on power-up
•
Supports hot insertion
•
Low stand-by current
•
Operating power supply voltage range of 2.3 V to 5.5 V
•
5 V tolerant Inputs
•
0 to 400 kHz clock frequency
•
ESD protection exceeds 2000 V HBM per JESD22-A114,
100 V MM per JESD22-A115 and 1000 V per JESD22-C101
SW00491
Figure 1. Pin configuration
PIN DESCRIPTION
PIN
NUMBER
1
2
3
4
5
6
7
8
SYMBOL
SCL
SDA
V
DD
SD0
SC0
V
SS
SD1
SC1
FUNCTION
Serial clock line
Serial data line
Supply voltage
Serial data 0
Serial clock 0
Supply ground
Serial data 1
Serial clock 1
•
Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA
•
Package Offer:
SO8, TSSOP8
DESCRIPTION
The PCA9540 is a 1-of-2 bi-directional translating multiplexer,
controlled via the I
2
C bus. The SCL/SDA upstream pair fans out to
two SCx/SDx downstream pairs, or channels. Only one SCx/SDx
channel is selected at a time, determined by the contents of the
programmable control register.
A power-on reset function puts the registers in their default state and
initializes the I
2
C state machine with no channels selected.
The pass gates of the multiplexer are constructed such that the V
DD
pin can be used to limit the maximum high voltage which will be
passed by the PCA9540. This allows the use of different bus
voltages on each SCx/SDx pair, so that 1.8 V, 2.5, or 3.3 V parts can
communicate with 5 V parts without any additional protection.
External pull-up resistors can pull the bus up to the desired voltage
level for this channel. All I/O pins are 5 V tolerant.
ORDERING INFORMATION
PACKAGES
8-Pin Plastic SO
TEMPERATURE RANGE
–40 to +85
°C
ORDER CODE
PCA9540D
DRAWING NUMBER
SOT96-1
SOT505-1
8-Pin Plastic TSSOP
–40 to +85
°C
PCA9540DP
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
2002 May 13
2
853–2185 28186
Philips Semiconductors
Product data
2-channel I
2
C multiplexer
PCA9540
BLOCK DIAGRAM
PCA9540
SC0
SC1
SD0
SD1
SWITCH CONTROL LOGIC
V
SS
V
DD
Power-on
Reset
SCL
Input
Filter
SDA
I
2
C-Bus
Control
SW00834
Figure 2. Block diagram
2002 May 13
3
Philips Semiconductors
Product data
2-channel I
2
C multiplexer
PCA9540
DEVICE ADDRESSING
Following a START condition the bus master must output the
address of the slave it is accessing. The address of the PCA9540 is
shown in Figure 3.
VOLTAGE TRANSLATION
The pass gate transistors of the PCA9540 are constructed such that
the V
DD
voltage can be used to limit the maximum voltage that will
be passed from one I
2
C bus to another.
1
1
1
0
0
0
0
R/W
5.0
V
pass
vs. V
DD
FIXED
SW00713
4.5
MAXIMUM
4.0
TYPICAL
3.5
V
pass
3.0
2.5
2.0
Figure 3. Slave address
The last bit of the slave address defines the operation to be
performed. When set to logic 1, a read is selected while a logic 0
selects a write operation.
CONTROL REGISTER
Following the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9540 which will be stored
in the Control Register. If multiple bytes are received by the
PCA9540, it will save the last byte received. This register can be
written and read via the I
2
C bus.
CHANNEL SELECTION BITS
(READ/WRITE)
7
X
6
X
5
X
4
X
3
X
2
B2
1
B1
0
B0
1.5
1.0
2.0
2.5
3.0
3.5
4.0
V
DD
4.5
MINIMUM
5.0
5.5
SW00820
Figure 5. V
pass
voltage
Figure 5 shows the voltage characteristics of the pass gate
transistors (note that the graph was generated using the data
specified in the DC Characteristics section of this datasheet). In
order for the PCA9540 to act as a voltage translator, the V
pass
voltage should be equal to, or lower than the lowest bus voltage. For
example, if the main bus was running at 5 V, and the downstream
buses were 3.3 V and 2.7 V, then V
pass
should be equal to or below
2.7 V to effectively clamp the downstream bus voltages. Looking at
Figure 5, we see that V
pass
(max.) will be at 2.7 V when the
PCA9540 supply voltage is 3.5 V or lower so the PCA9540 supply
voltage could be set to 3.3 V. Pull-up resistors can then be used to
bring the bus voltages to their appropriate levels (see Figure 12).
More Information can be found in Application Note AN262
PCA954X
family of I
2
C/SMBus multiplexers and switches.
ENABLE BIT
SW00839
Figure 4. Control register
CONTROL REGISTER DEFINITION
A SCx/SDx downstream pair, or channel, is selected by the contents
of the control register. This register is written after the PCA9540 has
been addressed. The 2 LSBs of the control byte are used to
determine which channel is to be selected. When a channel is
selected, the channel will become active after a stop condition has
been placed on the I
2
C bus. This ensures that all SCx/SDx lines will
be in a HIGH state when the channel is made active, so that no
false conditions are generated at the time of connection.
Table 1. Control Register; Write — Channel Selection/
Read — Channel Status
D7
X
X
X
X
D6
X
X
X
X
D5
X
X
X
X
D4
X
X
X
X
D3
X
X
X
X
B2
0
1
1
1
B1
X
0
0
1
B0
X
0
1
X
COMMAND
No channel selected
Channel 0 enabled
Channel 1 enabled
No channel selected
POWER-ON RESET
When power is applied to V
DD
, an internal Power On Reset holds
the PCA9540 in a reset state until V
DD
has reached V
POR
. At this
point, the reset condition is released and the PCA9540 registers and
I
2
C state machine are initialized to their default states, all zeroes
causing all the channels to be deselected.
2002 May 13
4
Philips Semiconductors
Product data
2-channel I
2
C multiplexer
PCA9540
CHARACTERISTICS OF THE I
2
C-BUS
The
is for 2-way, 2-line communication between different ICs
or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.
I
2
C-bus
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P)
(see Figure 7).
Bit transfer
One data bit is transferred during each clock pulse. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (see FIgure 6).
System configuration
A device generating a message is a ‘transmitter’, a device receiving
is the ‘receiver’. The device that controls the message is the
‘master’ and the devices which are controlled by the master are the
‘slaves’ (see Figure 8).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
SW00363
Figure 6. Bit transfer
SDA
SDA
SCL
S
START condition
P
STOP condition
SCL
SW00365
Figure 7. Definition of start and stop conditions
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
I
2
C
MULTIPLEXER
SLAVE
SW00366
Figure 8. System configuration
2002 May 13
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
