MC54/74F164
8-BIT SERIAL-IN, PARALLEL-OUT
SHIFT REGISTER
The MC54/74F164 is a high-speed 8-bit serial-in/parallel-out shift register.
Serial data is entered through a 2-input AND gate synchronous with the
LOW-to-HIGH transition of the clock. The device features an asynchronous
Master Reset which clears the register, setting all outputs LOW independent
of the clock.
8-BIT SERIAL-IN, PARALLEL-OUT
SHIFT REGISTER
FAST™ SHOTTKY TTL
•
•
•
•
Typical Shift Frequency of 90 MHz
Asynchronous Master Reset
Gated Serial Data Input
Fully Synchronous Data Transfers
J SUFFIX
CERAMIC
CASE 632-08
1
14
CONNECTION DIAGRAM
VCC
14
Q7
13
Q6
12
Q5
11
Q4
10
MR
9
CP
8
14
1
N SUFFIX
PLASTIC
CASE 646-06
1
A
2
B
3
Q0
4
Q1
5
Q2
6
Q3
7
GND
14
1
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
MC54FXXXJ
MC74FXXXN
MC74FXXXD
Inputs
Operating Mode
Reset (Clear)
Shift
MR
L
H
H
H
H
A
X
l
l
h
h
B
X
l
h
l
h
Q0
L
L
L
L
H
Outputs
Q1 –Q7
L–L
q0–q6
q0–q6
q0–q6
q0–q6
1
2
8
A
B
CP
MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
9 3 4 5 6 10 11 12 13
VCC = PIN 14
GND = PIN 7
Ceramic
Plastic
SOIC
MODE SELECT TABLE
LOGIC SYMBOL
H(h) = HIGH Voltage Levels
L(l) = LOW Voltage Levels
X = Don’t Care
qn = Lower case letters indicate the state of the referenced input or output one setup time prior to
the LOW-to-HIGH clock transition.
FAST AND LS TTL DATA
4-79
MC54/74F164
LOGIC DIAGRAM
A
B
D
Q
CD
D
Q
CD
D
Q
CD
D
Q
CD
D
Q
CD
D
Q
CD
D
Q
CD
D
Q
CD
CP
MR
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
FUNCTIONAL DESCRIPTION
The F164 is an edge-triggered 8-bit shift register with se-
rial data entry and an output from each of the eight stages.
Data is entered serially through one of two inputs (A or B); ei-
ther of these inputs can be used as an active HIGH Enable
for data entry through the other input. An unused input must
be tied HIGH.
GUARANTEED OPERATING RANGES
Symbol
VCC
TA
Supply Voltage
Operating Ambient Temperature Range
Parameter
54, 74
54
74
IOH
IOL
Output Current
High
Output Current
Low
54, 74
54, 74
Min
4.5
–55
0
Typ
5.0
25
25
Max
5.5
125
70
–1.0
20
mA
mA
Unit
V
°C
Each LOW-to-HIGH transition on the Clock (CP) input
shifts data one place to the right and enters into Q0 the logical
AND of the two data inputs (A
•
B) that existed before the rising
clock edge. A LOW level on the Master Reset (MR) input over-
rides all other inputs and clears the register asynchronously,
forcing all Q outputs LOW.
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
VIH
VIL
VIK
VOH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54, 74
74
VOL
IIH
Output LOW Voltage
Input HIGH Current
2.5
2.7
0.5
20
0.1
IIL
IOS
ICC
Input LOW Current
Output Short Circuit Current (Note 2)
Power Supply Current
–60
35
–0.6
–150
55
Min
2.0
0.8
–1.2
Typ
Max
Unit
V
V
V
V
V
V
µA
mA
mA
mA
mA
Test Conditions
Guaranteed Input HIGH Voltage
Guaranteed Input LOW Voltage
VCC = MIN, IIN = –18 mA
IOH = –1.0 mA
IOH = –1.0 mA
IOL = 20 mA
VCC = MIN
VCC = 4.75 V
VCC = MIN
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V
VCC = MAX, VIN = 0.5 V
VCC = MAX, VOUT = 0 V
A, B = GND, VCC = MAX
CP = HIGH, MR = GND
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type.
2. Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA
4-80