INTEGRATED CIRCUITS
74F676
16-bit serial/parallel-in, serial-out shift
register (3-State)
Product specification
IC15 Data Handbook
1989 Apr 18
Philips
Semiconductors
Philips Semiconductors
Product specification
16-bit serial/parallel-in, serial-out shift register (3-State)
74F676
FEATURES
•
16-bit parallel-to-serial conversion
•
16-bit serial-in, serial-out
•
Chip select control
•
Power supply current 48mA typical
•
Shift frequency 110MHz tyical
•
Available in 300mil-wide 24-pin Slim DIP package
DESCRIPTION
The 74F676 contains 16 flip-flops with provision for synchronous
parallel or serial entry and serial output. When the mode (M) input is
High, information present on the parallel data (D0–D15) inputs is
entered on the falling edge of the clock pulse (CP) input signal.
When M is Low, data is shifted out of the most significant bit position
while information present on the serial (SI) input shifts into the least
significant bit position. A High signal on the chip select (CS) input
prevents both parallel and serial operations.
The 16 bit shift register operates in one of three modes, as indicated
in the shift register Function Table.
Hold:
A High signal on the Chip Select (CS) input prevents clocking
and data is stored in the 16 registers.
Serial load:
Data present on the SI pin shifts into the register on the
falling edge of CP. Data enters the Q0 position and shifts toward
Q15 on successive clocks finally appearing on the SO pin.
Parallel load:
Data present on D0–D15 is entered into the register
on the falling edge of CP. The SO output represents the Q15 register
output.
To prevent false clocking, CP must be Low during a Low-to-High
transition of CS.
PIN CONFIGURATION
CS
CP
NC
SI
M
SO
D0
D1
D2
1
2
3
4
5
6
7
8
9
24 V
CC
23 D15
22 D14
21 D13
20 D12
19 D11
18 D10
17 D9
16 D8
15 D7
14 D6
13 D5
D3 10
D4 11
GND 12
SF01209
TYPE
74F676
TYPICAL f
MAX
110MHz
TYPICAL SUPPLY
CURRENT
(TOTAL)
48mA
ORDERING INFORMATION
DESCRIPTION
24-Pin Plastic Slim
DIP (300mil)
24-Pin Plastic SOL
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
N74F676N
N74F676D
PKG DWG #
SOT222-1
SOT137-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
D0–D15
SI
CS
CP
M
SO
Parallel data inputs
Serial data input
Chip Select input (active Low)
Clock Pulse input (active falling edge)
Mode select input
Serial data output
DESCRIPTION
74F(U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
1mA/20mA
NOTE:
One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
1990 Apr 18
2
853–0284 99394
Philips Semiconductors
Product specification
16-bit serial/parallel-in, serial-out shift register (3-State)
74F676
LOGIC SYMBOL
4
7
8
9 10 11 13 14 15 16 17
18
19
20
21
22
23
LOGIC DIAGRAM
CP
CS
M
2
1
5
4
7
D
CP
Q
SI D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
1
2
5
CS
CP
M
SO
D1
8
D
CP
Q
SI
D0
V
CC
= Pin 24
GND = Pin 12
CP
6
SF01210
D2
9
D
Q
LOGIC SYMBOL (IEEE/IEC)
D3
SRG16
5
0
M
1
1
2
7
8
9
10
11
13
14
15
16
17
18
19
20
21
22
23
4
2, 3D
1, 3D
6
D10
18
D
D9
17
D
D8
16
D
D7
15
D
D6
14
D
&
C3/1
0
2
D4
10
D
CP
Q
CP
11
D
Q
CP
2, 3D
D5
13
D
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
SF01211
D11
19
D
Q
CP
FUNCTION TABLE
CONTROL INPUTS
CS
H
L
H
L
X
↓
=
=
=
=
M
X
L
CP
X
↓
Hold
Shift/Serial load
OPERATING MODE
D12
20
D
Q
CP
D13
21
D
Q
L
H
↓
Parallel load
High voltage level
Low voltage level
Don’t care
High-to-Low transition of clock input
CP
D14
22
D
Q
CP
D15
V
CC
= Pin 24
GND = Pin 12
23
D
Q
6
SO
SF01212
1990 Apr 18
3
Philips Semiconductors
Product specification
16-bit serial/parallel-in, serial-out shift register (3-State)
74F676
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5.0
–0.5 to +V
CC
40
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
IH
V
IL
I
IK
I
OH
I
OL
T
amb
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
Operating free-air temperature range
0
PARAMETER
LIMITS
MIN
4.5
2.0
0.8
–18
–1
20
70
NOM
5.0
MAX
5.5
UNIT
V
V
V
mA
mA
mA
°C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
SYMBOL
PARAMETER
TEST
CONDITIONS
NO TAG
MIN
V
CC
= MIN, V
IL
= MAX,
,
,
V
IH
= MIN, I
OH
= MAX
V
CC
= MIN, V
IL
= MAX,
,
,
V
IH
= MIN, I
OL
= MAX
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX
V
CC
= MAX
–60
48
±10%V
CC
±5%V
CC
±10%V
CC
±5%V
CC
2.5
2.7
3.4
0.30
0.30
–0.73
0.50
0.50
–1.2
100
20
–0.6
–150
72
TYP
NO TAG
UNIT
MAX
V
V
V
V
V
µA
µA
mA
mA
mA
V
O
OH
High-level
High level output voltage
V
O
OL
V
IK
I
I
I
IH
I
IL
I
OS
I
CC
Low-level
Low level output voltage
Input clamp voltage
Input current at maximum input voltage
High-level input current
Low-level input current
Short-circuit output current
NO TAG
Supply current (total)
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value under the recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25°C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
should be performed last.
1990 Apr 18
4
Philips Semiconductors
Product specification
16-bit serial/parallel-in, serial-out shift register (3-State)
74F676
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
T
amb
= +25°C
V
CC
= +5.0V
C
L
= 50pF, R
L
= 500Ω
MIN
f
MAX
t
PLH
t
PHL
Maximum clock frequency
Propagation delay
CP to SO
Waveform
NO TAG
Waveform
NO TAG
100
4.5
5.0
TYP
110
8.0
7.0
11.0
12.5
MAX
T
amb
= 0°C to +70°C
V
CC
= +5.0V
±
10%
C
L
= 50pF, R
L
= 500Ω
MIN
90
4.5
5.0
12.0
13.5
MAX
MHz
ns
ns
UNIT
AC SETUP REQUIREMENTS
LIMITS
S
O
SYMBOL
PARAMETER
S CONDITION
O
TEST CO
T
amb
= +25°C
V
CC
= +5.0V
C
L
= 50pF, R
L
= 500Ω
MIN
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
s
(L)
t
h
(H)
t
w
(H)
t
w
(L)
Setup time, High or Low
SI to CP
Hold time, High or Low
SI to CP
Setup time, High or Low
Dn to CP
Hold time, High or Low
Dn to CP
Setup time, High or Low
M to CP
Hold time, High or Low
M to CP
Setup time, Low
CS to CP
Hold time, High
CS to CP
CP Pulse width,
High or Low
Waveform 2
Waveform 2
Waveform 2
Waveform 2
Waveform 2
Waveform 2
Waveform 2
Waveform 2
Waveform NO TAG
4.0
4.0
4.0
4.0
3.0
3.0
4.0
4.0
8.0
8.0
2.0
2.0
10.0
10.0
4.0
6.0
TYP
MAX
T
amb
= 0°C to +70°C
V
CC
= +5.0V
±
10%
C
L
= 50pF, R
L
= 500Ω
MIN
4.0
4.0
4.0
4.0
3.0
3.0
4.0
4.0
8.0
8.0
2.0
2.0
10.0
10.0
4.0
6.0
MAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT
AC WAVEFORMS
For all waveforms, V
M
= 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/f
MAX
CP
Dn, CS,
M, SI
V
M
t
w
(L)
t
PLH
SO
V
M
V
M
t
w
(H)
t
PHL
CP
V
M
V
M
V
M
V
M
V
M
t
s
(H)
V
M
t
h
(H)
V
M
t
s
(L)
V
M
t
h
(L)
SF01213
SF01214
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
Waveform 2. Setup and Hold Times
1990 Apr 18
5
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