INTEGRATED CIRCUITS
74F175*,
74F175A
Quad D flip-flop
* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.
Product specification
IC15 Data Handbook
1996 Mar 12
Philips
Semiconductors
Philips Semiconductors
Product specification
Quad D flip-flop
74F175A
FEATURES
•
Four edge-triggered D-type flip-flops
•
Buffered common clock
•
Buffered asynchronous Master Reset
•
True and complementary outputs
•
Industrial temperature range available (–40°C to +85°C)
•
PNP light loading inputs
DESCRIPTION
The 74F175A is a quad, edge-triggered D-type flip-flop with
individual D inputs and both Q and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset (clear) all
flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
All Q outputs will be forced Low independently of clock or data
inputs by a Low voltage level on the MR input. The device is useful
for applications where both true and complementary outputs are
required, and the CP and MR are common to all storage elements.
PIN CONFIGURATION
MR
1
16 V
CC
15 Q3
14 Q3
13 D3
12 D2
11 Q2
10 Q2
9 CP
Q0 2
Q0 3
D0 4
D1 5
Q1 6
Q1 7
GND
8
SF00718
TYPE
74F175A
TYPICAL f
max
160MHz
TYPICAL SUPPLY
CURRENT (TOTAL)
22mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
74F175AN
74F175AD
PKG. DWG. #
16-pin plastic DIP
16-pin plastic SO
SOT38-4
SOT109-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
D0 – D3
MR
CP
Q0–Q3
Q0–Q3
Data inputs
Master reset input (active–Low)
Clock input (active rising edge)
True outputs
Complementary outputs
DESCRIPTION
74F175A
74F175A
74F175A
74F (U.L.)
HIGH/LOW
1.0/0.033
1.0/0.033
1.0/0.033
50/33
50/33
LOAD VALUE
HIGH/LOW
20µA/20µA
20µA/20µA
20µA/20µA
1.0mA/20mA
1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
1996 Mar 12
2
853–0047 16555
Philips Semiconductors
Product specification
Quad D flip-flop
74F175A
LOGIC SYMBOL
4
5
12 13
IEC/IEEE SYMBOL
1
9
R
C1
2
D0 D1 D2 D3
4
1D
3
7
5
6
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
10
12
11
15
2
3
7
6
10 11 15 14
13
14
9
1
CP
MR
V
CC
= Pin 16
GND = Pin 8
SF00719
SF00720
LOGIC DIAGRAM
D0
4
CP
9
D1
5
D2
12
D3
13
D
Q
D
Q
D
Q
D
Q
CP
RD
MR
V
CC
= Pin 16
GND = Pin 8
1
3
2
Q0 Q0
CP
RD
CP
RD
CP
Q
RD
6
Q1
7
Q1
11
Q2
Q2
10
Q3
14
15
Q3
SF00721
FUNCTION TABLE
INPUTS
MR
L
H
H
CP
X
↑
↑
Dn
X
h
I
OUTPUTS
Q
n
L
H
L
Q
n
H
L
H
OPERATING
MODE
Reset (clear)
Load “1”
Load “0”
H = High voltage level
h = High state must be present one setup time before the
Low-to-High clock transition
L = Low voltage level
l = Low state must be present one setup time before the
Low-to-High clock transition
X = Don’t care
↑
= Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
b
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Commercial range
O erating
Operating free air tem erature range
temperature
Industrial range
Storage temperature range
–40 to +85
–65 to +150
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V
CC
40
0 to +70
UNIT
V
V
mA
V
mA
°
C
°
C
°
C
1996 Mar 12
3
Philips Semiconductors
Product specification
Quad D flip-flop
74F175A
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN
V
CC
V
IH
V
IL
I
IK
I
OH
I
OL
T
amb
b
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
Commercial range
Operating free air temperature range
Industrial range
0
–40
4.5
2.0
0.8
–18
–1
20
+70
+85
LIMITS
NOM
5.0
MAX
5.5
V
V
V
mA
mA
mA
UNIT
°
C
°
C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
CONDITIONS
1
V
OH
V
OL
High-level out ut voltage
output
Low-level output voltage
V
CC
= MIN, V
IL
= MAX,
V
IH
= MIN, I
OH
= MAX
V
CC
= MIN, V
IL
= MAX,
V
IH
= MIN, I
OL
= MAX
V
CC
= MIN, I
I
= I
IK
V
CC
= 0.0V, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX
V
CC
= MAX
74F175A
74F175A
–60
22
"10%V
CC
"5%V
CC
"10%V
CC
"5%V
CC
MIN
2.5
2.7
3.4
0.30
0.30
–0.73
0.5
0.5
–1.2
100
20
–20
–150
31
V
V
µA
µA
µA
mA
mA
V
LIMITS
TYP
2
MAX
UNIT
V
IK
I
I
I
IH
I
IL
I
OS
I
CC
Input clamp voltage
Input current at maximum input voltage
High-level input current
Low-level input current
Short-circuit output current
3
Supply current (total)
Notes to DC electrical characteristics
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
°
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
AC ELECTRICAL CHARACTERISTICS FOR 74F175A
LIMITS
T
amb
= 25
°
C
SYMBOL
PARAMETER
TEST
CONDITION
MIN
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PHL
1996 Mar 12
Maximum clock
frequency
Propagation delay
CP to Qn or Qn
Propagation delay
MR to Qn
Propagation delay
MR to Qn
Waveform 1
Waveform 1
Waveform 3
Waveform 3
140
3.0
4.5
4.5
4.5
V
CC
= +5V
C
L
= 50pF,
R
L
= 500Ω
TYP
160
4.0
6.0
6.5
6.0
6.5
8.5
9.0
8.0
MAX
T
amb
= 0
°
C to +70
°
C
V
CC
= +5.0V
±
10%
C
L
= 50pF,
R
L
= 500Ω
MIN
125
2.5
4.0
4.5
4.0
7.5
9.0
10.0
9.0
MAX
T
amb
=
*40
°
C to +85
°
C
V
CC
= +5.0V
±
10%
C
L
= 50pF,
R
L
= 500Ω
MIN
110
2.5
4.0
4.5
4.0
8.0
10.0
11.0
10.0
MAX
MHz
ns
ns
ns
UNIT
4
Philips Semiconductors
Product specification
Quad D flip-flop
74F175A
AC SETUP REQUIREMENTS FOR 74F175A
LIMITS
T
amb
= 25
°
C
SYMBOL
PARAMETER
TEST
CONDITION
MIN
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
t
w
(L)
t
REC
Setup time, High or Low
Dn to CP
Hold time, High or Low
Dn to CP
CP Pulse width
High or Low
MR Pulse width
Low
Recovery time
MR to CP
Waveform 2
Waveform 2
Waveform 1
Waveform 3
Waveform 3
3.0
3.0
0.0
0.0
3.0
4.0
3.5
4.0
V
CC
= +5V
C
L
= 50pF,
R
L
= 500Ω
TYP
MAX
T
amb
= 0
°
C to +70
°
C
V
CC
= +5.0V
±
10%
C
L
= 50pF,
R
L
= 500Ω
MIN
3.5
3.5
0.0
0.0
3.5
5.0
3.5
4.5
MAX
T
amb
=
*40
°
C to +85
°
C
V
CC
= +5.0V
±
10%
C
L
= 50pF,
R
L
= 500Ω
MIN
4.0
4.0
0.0
0.0
4.0
5.5
4.0
5.0
MAX
ns
ns
ns
ns
ns
UNIT
AC WAVEFORMS
For all waveforms, V
M
= 1.3V.
1/f
max
MR
CP
V
M
t
w
(H)
t
PHL
V
M
t
PLH
Q
n
V
M
t
w
(L)
t
PLH
CP
V
M
t
PHL
t
PHL
Q
n
t
PLH
V
M
V
M
V
M
t
w
(L)
t
REC
V
M
V
M
V
M
Q
n
V
M
SF00722
Q
n
V
M
Waveform 1. Propagation delay for clock input to output, clock
pulse width, and maximum clock frequency
SF00723
Waveform 3. Master Reset pulse width, Master Reset to output
delay and Master Reset to Clock recovery time
Dn
V
M
t
s
(H)
CP
V
M
t
h
(H)
V
M
t
s
(L)
V
M
t
h
(L)
V
M
V
M
SF00191
Waveform 2. Data setup time and hold times
1996 Mar 12
5
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