INTEGRATED CIRCUITS
DATA SHEET
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The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4053B
MSI
Triple 2-channel analogue
multiplexer/demultiplexer
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
Triple 2-channel analogue
multiplexer/demultiplexer
DESCRIPTION
The HEF4053B is a triple 2-channel analogue
multiplexer/demultiplexer with a common enable input (E).
Each multiplexer/demultiplexer has two independent
inputs/outputs (Y
0
and Y
1
), a common input/output (Z),
and select inputs (S
n
). Each also contains two-bidirectional
analogue switches, each with one side connected to an
independent input/output (Y
0
and Y
1
) and the other side
connected to a common input/output (Z).
HEF4053B
MSI
With E LOW, one of the two switches is selected (low
impedance ON-state) by S
n
. With E HIGH, all switches are
in the high impedance OFF-state, independent of S
A
to S
C
.
V
DD
and V
SS
are the supply voltage connections for the
digital control inputs (S
A
to S
C
and E).
The V
DD
to V
SS
range is 3 to 15 V. The analogue
inputs/outputs (Y
0
, Y
1
and Z) can swing between V
DD
as a
positive limit and V
EE
as a negative limit. V
DD
−V
EE
may not
exceed 15 V.
For operation as a digital multiplexer/demultiplexer, V
EE
is
connected to V
SS
(typically ground).
Fig.1 Functional diagram.
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
Triple 2-channel analogue
multiplexer/demultiplexer
PINNING
Y
0A
to Y
0C
Y
1A
to Y
1C
S
A
to S
C
E
Z
A
to Z
C
FUNCTION TABLE
Fig.2 Pinning diagram.
E
L
HEF4053BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4053BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4053BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
Notes
L
H
INPUTS
S
n
L
H
X
HEF4053B
MSI
independent inputs/outputs
independent inputs/outputs
select inputs
enable input (active LOW)
common inputs/outputs
CHANNEL
ON
Y
0n
−Z
n
Y
1n
−Z
n
none
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
Fig.3 Schematic diagram (one switch).
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage (with reference to V
DD
)
Note
1. To avoid drawing V
DD
current out of terminal Z, when switch current flows into terminals Y, the voltage drop across
the bidirectional switch must not exceed 0,4 V. If the switch current flows into terminal Z, no V
DD
current will flow out
of terminals Y, in this case there is no limit for the voltage drop across the switch, but the voltages at Y and Z may
not exceed V
DD
or V
EE
.
January 1995
3
V
EE
−18
to
+
0,5 V
Philips Semiconductors
Product specification
Triple 2-channel analogue
multiplexer/demultiplexer
HEF4053B
MSI
Fig.4 Logic diagram.
January 1995
4
Philips Semiconductors
Product specification
Triple 2-channel analogue
multiplexer/demultiplexer
DC CHARACTERISTICS
T
amb
= 25
°C
V
DD
−V
EE
V
5
ON resistance
10
15
5
ON resistance
10
15
5
ON resistance
‘∆’ ON resistance
between any two
channels
OFF-state leakage
current, all
channels OFF
OFF-state leakage
current, any
channel
10
15
5
10
15
5
10
15
5
10
15
I
OZY
I
OZZ
−
−
−
−
−
−
∆R
ON
R
ON
R
ON
R
ON
SYMBOL
TYP.
350
80
60
115
50
40
120
65
50
25
10
5
MAX.
2500
245
175
340
160
115
365
200
155
−
−
−
−
−
1000
−
−
200
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
nA
nA
nA
nA
nA
nA
E at V
SS
E at V
DD
HEF4053B
MSI
CONDITIONS
V
is
= 0 to V
DD
−V
EE
see Fig.6
V
is
= 0
see Fig.6
V
is
= V
DD
−V
EE
see Fig.6
V
is
= 0 to V
DD
−V
EE
see Fig.6
Fig.5 Operating area as a function of the supply voltages.
January 1995
5
FPGA/CPLD
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