PD - 97129A
IRFR1018EPbF
IRFU1018EPbF
Applications
l
High Efficiency Synchronous Rectification in
SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
l
Hard Switched and High Frequency Circuits
HEXFET
®
Power MOSFET
D
G
S
Benefits
l
Improved Gate, Avalanche and Dynamic
dv/dt Ruggedness
l
Fully Characterized Capacitance and
Avalanche SOA
l
Enhanced body diode dV/dt and dI/dt
Capability
V
DSS
R
DS(on)
typ.
max.
I
D (Silicon Limited)
I
D (Package Limited)
60V
7.1m
:
8.4m
:
79A
c
56A
D-Pak
IRFR1018EPbF
I-Pak
IRFU1018EPbF
G
D
S
Gate
Drain
Max.
79c
56c
56
315
110
0.76
± 20
21
-55 to + 175
300
Source
Units
Absolute Maximum Ratings
Symbol
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
D
@ T
C
= 25°C
I
DM
P
D
@T
C
= 25°C
V
GS
dv/dt
T
J
T
STG
Parameter
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Wire Bond Limited)
Pulsed Drain Current
d
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery
f
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
A
W
W/°C
V
V/ns
°C
Avalanche Characteristics
E
AS (Thermally limited)
I
AR
E
AR
Single Pulse Avalanche Energy
e
Avalanche Current
d
Repetitive Avalanche Energy
g
88
47
11
mJ
A
mJ
Thermal Resistance
Symbol
R
θJC
R
θJA
R
θJA
Parameter
Junction-to-Case
k
Junction-to-Ambient (PCB Mount)
jk
Junction-to-Ambient
k
Typ.
–––
–––
–––
Max.
1.32
50
110
Units
°C/W
Notes
through
are on page 2
www.irf.com
1
4/21/09
IRFR/U1018EPbF
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
ΔV
(BR)DSS
/ΔT
J
R
DS(on)
V
GS(th)
I
DSS
I
GSS
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Min. Typ. Max. Units
60
––– –––
––– 0.073 –––
–––
7.1
8.4
2.0
–––
4.0
––– –––
20
––– ––– 250
––– ––– 100
––– ––– -100
Conditions
V V
GS
= 0V, I
D
= 250μA
V/°C Reference to 25°C, I
D
= 5mAd
mΩ V
GS
= 10V, I
D
= 47A
g
V V
DS
= V
GS
, I
D
= 100μA
μA
V
DS
= 60V, V
GS
= 0V
V
DS
= 48V, V
GS
= 0V, T
J
= 125°C
nA V
GS
= 20V
V
GS
= -20V
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
gfs
Q
g
Q
gs
Q
gd
Q
sync
R
G(int)
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
C
oss
eff. (ER)
C
oss
eff. (TR)
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Q
g
- Q
gd
)
Internal Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Min. Typ. Max. Units
110
–––
–––
–––
–––
–––
Conditions
V
DS
= 50V, I
D
= 47A
I
D
= 47A
V
DS
= 30V
V
GS
= 10V
g
I
D
= 47A, V
DS
=0V, V
GS
= 10V
V
DD
= 39V
I
D
= 47A
R
G
= 10Ω
V
GS
= 10V
g
V
GS
= 0V
V
DS
= 50V
ƒ = 1.0MHz
V
GS
= 0V, V
DS
= 0V to 60V
i
V
GS
= 0V, V
DS
= 0V to 60V
h
–––
46
10
12
34
0.73
13
35
55
46
2290
270
130
390
630
–––
69
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
S
nC
Ω
–––
–––
–––
–––
–––
–––
–––
Effective Output Capacitance (Energy Related)h –––
–––
Effective Output Capacitance (Time Related)g
ns
pF
Diode Characteristics
Symbol
I
S
I
SM
V
SD
t
rr
Q
rr
I
RRM
t
on
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
d
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
Forward Turn-On Time
Min. Typ. Max. Units
–––
–––
–––
–––
79c
315
A
Conditions
MOSFET symbol
showing the
integral reverse
G
S
D
––– –––
1.3
V
–––
26
39
ns
–––
31
47
–––
24
36
nC
T
J
= 125°C
–––
35
53
–––
1.8
–––
A T
J
= 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
p-n junction diode.
T
J
= 25°C, I
S
= 47A, V
GS
= 0V
g
T
J
= 25°C
V
R
= 51V,
I
F
= 47A
T
J
= 125°C
di/dt = 100A/μs
g
T
J
= 25°C
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Bond wire current limit is 56A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements.
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.08mH
R
G
= 25Ω, I
AS
= 47A, V
GS
=10V. Part not recommended for
use above this value.
I
SD
≤
47A, di/dt
≤
1668A/μs, V
DD
≤
V
(BR)DSS
, T
J
≤
175°C.
Pulse width
≤
400μs; duty cycle
≤
2%.
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
R
θ
is measured at T
J
approximately 90°C.
2
www.irf.com
IRFR/U1018EPbF
1000
TOP
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
1000
TOP
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
ID, Drain-to-Source Current (A)
100
ID, Drain-to-Source Current (A)
BOTTOM
100
BOTTOM
4.5V
10
10
4.5V
≤60μs
PULSE WIDTH
Tj = 25°C
1
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
1
0.1
1
≤60μs
PULSE WIDTH
Tj = 175°C
10
100
VDS, Drain-to-Source Voltage (V)
Fig 1.
Typical Output Characteristics
1000
RDS(on) , Drain-to-Source On Resistance
(Normalized)
Fig 2.
Typical Output Characteristics
2.5
ID = 47A
2.0
VGS = 10V
ID, Drain-to-Source Current (A)
100
TJ = 175°C
10
1.5
1
TJ = 25°C
VDS = 25V
1.0
≤60μs
PULSE WIDTH
0.1
2
3
4
5
6
7
8
9
0.5
-60 -40 -20 0 20 40 60 80 100120140160180
TJ , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
Fig 3.
Typical Transfer Characteristics
4000
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Fig 4.
Normalized On-Resistance vs. Temperature
16
VGS, Gate-to-Source Voltage (V)
ID= 47A
VDS = 48V
VDS = 30V
VDS = 12V
3000
C, Capacitance (pF)
Ciss
2000
12
8
1000
Coss
Crss
1
10
VDS , Drain-to-Source Voltage (V)
100
4
0
0
0
10
20
30
40
50
60
QG Total Gate Charge (nC)
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
www.irf.com
3
IRFR/U1018EPbF
1000
10000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS (on)
100
1000
TJ = 175°C
100
1msec
10
100μsec
TJ = 25°C
10
LIMITED BY PACKAGE
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
0.1
1
1
VGS = 0V
0.1
0.0
0.5
1.0
1.5
2.0
VSD , Source-to-Drain Voltage (V)
1
DC
10
100
0.1
VDS , Drain-toSource Voltage (V)
Fig 7.
Typical Source-Drain Diode Forward Voltage
80
LIMITED BY PACKAGE
60
V(BR)DSS, Drain-to-Source Breakdown Voltage (V)
Fig 8.
Maximum Safe Operating Area
80
Id = 5mA
ID, Drain Current (A)
75
40
70
20
65
0
25
50
75
100
125
150
175
TC, Case Temperature (°C)
60
-60 -40 -20 0 20 40 60 80 100120140160180
TJ , Temperature ( °C )
Fig 9.
Maximum Drain Current vs. Case Temperature
0.8
Fig 10.
Drain-to-Source Breakdown Voltage
400
EAS, Single Pulse Avalanche Energy (mJ)
350
300
250
200
150
100
50
0
0.6
5.3A
11A
BOTTOM
47A
TOP
ID
Energy (μJ)
0.4
0.2
0.0
0
10
20
30
40
50
60
25
50
75
100
125
150
175
VDS, Drain-to-Source Voltage (V)
Starting TJ, Junction Temperature (°C)
4
Fig 11.
Typical C
OSS
Stored Energy
Fig 12.
Maximum Avalanche Energy vs. DrainCurrent
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IRFR/U1018EPbF
10
Thermal Response ( Z thJC )
1
D = 0.50
0.20
0.1
0.10
0.05
0.02
0.01
τ
J
τ
J
τ
1
τ
1
R
1
R
1
τ
2
R
2
R
2
R
3
R
3
τ
3
R
4
R
4
τ
C
τ
τ
4
τ
2
τ
3
τ
4
0.01
Ci=
τi/Ri
Ci i/Ri
Ri (°C/W)
0.026741
0.28078
0.606685
0.406128
τι
(sec)
0.000007
0.000091
0.000843
0.005884
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
ΔTj
= 150°C and
Tstart =25°C (Single Pulse)
Avalanche Current (A)
0.01
10
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
ΔΤ
j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14.
Typical Avalanche Current vs.Pulsewidth
100
EAR , Avalanche Energy (mJ)
80
TOP
Single Pulse
BOTTOM 10% Duty Cycle
ID = 47A
60
40
20
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
ΔT
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
175
0
25
50
75
100
125
150
Starting TJ , Junction Temperature (°C)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
DT/
Z
thJC
I
av
= 2DT/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Fig 15.
Maximum Avalanche Energy vs. Temperature
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