INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4016B
gates
Quadruple bilateral switches
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
Quadruple bilateral switches
DESCRIPTION
The HEF4016B has four independent analogue switches
(transmission gates). Each switch has two input/output
terminals (Y/Z) and an active HIGH enable input (E). When
E is connected to V
DD
a low impedance bidirectional path
between Y and Z is established (ON condition). When E is
connected to V
SS
the switch is disabled and a high
HEF4016B
gates
impedance between Y and Z is established (OFF
condition). Current through a switch will not cause
additional V
DD
current provided the voltage at the
terminals of the switch is maintained within the supply
voltage range; V
DD
≥
(V
Y
, V
Z
)
≥
V
SS
. Inputs Y and Z are
electrically equivalent terminals.
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
PINNING
E
0
to E
3
Y
0
to Y
3
Z
0
to Z
3
enable inputs
input/output terminals
input/output terminals
HEF4016BP(N): 14-lead DIL; plastic (SOT27-1)
HEF4016BD(F): 14-lead DIL; ceramic (cerdip) (SOT73)
HEF4016BT(D): 14-lead SO; plastic (SOT108-1)
( ): Package Designator North America
APPLICATION INFORMATION
Some examples of applications for the HEF4016B are:
•
Signal gating
•
Modulation
•
Demodulation
•
Chopper
Fig.3 Schematic diagram
(one switch).
January 1995
2
Philips Semiconductors
Product specification
Quadruple bilateral switches
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Power dissipation per switch
For other RATINGS see Family Specifications
DC CHARACTERISTICS
T
amb
= 25
°C;
V
SS
= 0 V (unless otherwise specified)
PARAMETER
V
DD
V
5
ON resistance
10
15
5
ON resistance
10
15
5
ON resistance
‘∆’ ON resistance
between any two
channels
10
15
5
10
15
∆R
ON
R
ON
R
ON
R
ON
SYMBOL
TYP.
8000
230
115
140
65
50
170
95
75
200
15
10
MAX.
−
690
350
425
195
145
515
285
220
−
−
−
UNIT
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
P
max.
HEF4016B
gates
100
mW
CONDITIONS
E
n
at V
IH
; V
is
= 0 to V
DD
; see Fig.4
E
n
at V
IH
; V
is
= V
SS
; see Fig.4
E
n
at V
IH
; V
is
= V
DD
; see Fig.4
E
n
at V
IH
; V
is
= 0 to V
DD
; see Fig.4
PARAMETER
V
DD
V
T
amb
(°C)
SYMBOL
−
I
DD
−
−
±
I
IN
−
−
I
OZ
−
−
−
V
IL
−
−
3,5
V
IH
7,0
11,0
−40
−
−
−
−
−
−
−
−
−
−
3,5
7,0
11,0
+
25
−
−
−
−
−
−
−
−
−
−
3,5
7,0
11,0
+
85
UNIT
µA
µA
µA
nA
nA
nA
nA
V
V
V
V
V
V
low-impedance
between Y and Z (ON
condition)
see R
ON
switch
CONDITION
MIN. MAX. MIN. MAX. MIN. MAX.
Quiescent
device
current
Input leakage
current at E
n
OFF-state leakage
current, any
channel OFF
E
n
input
voltage LOW
E
n
input
voltage HIGH
5
10
15
15
5
10
15
5
10
15
5
10
15
1,0
2,0
4,0
−
−
−
−
1,5
3,0
4,0
−
−
−
1,0
2,0
4,0
300
−
−
200
1,5
3,0
4,0
−
−
−
7,5
15,0
30,0
1000
−
−
−
1,5
3,0
4,0
−
−
−
V
SS
= 0; all valid
input combinations;
V
I
= V
SS
or V
DD
E
n
at V
SS
or V
DD
E
n
at V
IL
;
V
is
= V
SS
or V
DD
;
V
os
= V
DD
or V
SS
switch OFF; see
Fig.9 for I
OZ
January 1995
3
Philips Semiconductors
Product specification
Quadruple bilateral switches
HEF4016B
gates
Fig.4 Test set-up for measuring R
ON
.
E
n
>
V
IH
I
is
= 100
µA
V
SS
= 0 V
Fig.5 Typical R
ON
as a function of input voltage.
January 1995
4
Philips Semiconductors
Product specification
Quadruple bilateral switches
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°C;
input transition times
≤
20 ns
V
DD
V
Propagation delays
V
is
→
V
os
HIGH to LOW
5
10
15
5
LOW to HIGH
Output disable times
E
n
→
V
os
HIGH
5
10
15
5
LOW
Output enable times
E
n
→
V
os
HIGH
5
10
15
5
LOW
Distortion, sine-wave
response
Crosstalk between
any two channels
Crosstalk; enable
input to output
OFF-state
feed-through
ON-state frequency
response
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
t
PZL
t
PZH
40
20
15
40
20
15
−
0,08
0,04
−
1
−
−
50
−
−
1
−
−
90
−
80
40
30
80
40
30
ns
ns
ns
ns
ns
ns
%
%
%
MHz
MHz
MHz
mV
mV
mV
MHz
MHz
MHz
MHz
MHz
MHz
10
15
t
PLZ
t
PHZ
90
80
75
85
75
75
130
110
100
120
100
100
ns
ns
ns
ns
ns
ns
10
15
t
PLH
t
PHL
25
10
5
20
10
5
50
20
10
40
20
10
ns
ns
ns
ns
ns
ns
SYMBOL
TYP.
MAX.
HEF4016B
gates
note 1
note 1
note 2
note 2
note 2
note 2
note 3
note 4
note 5
note 6
note 7
January 1995
5
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