Product Specification
PE97042
Product Description
Peregrine’s PE97042 is a high-performance integer-N PLL
capable of frequency synthesis up to 3500 MHz. The
device is designed for superior phase noise performance
while providing an order of magnitude reduction in current
consumption, when compared with existing commercial
space PLLs.
The PE97042 features a ÷10/11 dual modulus prescaler,
counters, and a phase comparator as shown in Figure 1.
Counter values are programmable through a serial
interface, and can also be directly hard wired.
The PE97042 is optimized for commercial space
applications. Single Event Latch up (SEL) is physically
impossible and Single Event Upset (SEU) is better than
10
-9
errors per bit / day. It is manufactured on Peregrine’s
UltraCMOS™ process, a patented variation of silicon-on-
insulator (SOI) technology on a sapphire substrate, offering
excellent RF performance and intrinsic radiation tolerance.
3500 MHz UltraCMOS™ Integer-N PLL
Rad Hard for Space Applications
Features
•
Low Power: 45 mA Typical
•
3500 MHz operation
•
÷10/11 dual modulus prescaler
•
Phase detector output
•
Serial interface or hardwired
programmable
•
Ultra-Low Phase Noise: -216 dBc/Hz
•
SEU < 10
-9
errors / bit-day
•
100 Krad (Si) total dose
•
Easily modified to be pin compatible
with the PE9704, packaged in a 44-lead
CQFJ
(reference application note AN23
at www.psemi.com)
Figure 1. Block Diagram
F
IN
Prescaler
10 / 11
MSEL
Main
Counter
13
Serial
Control
3
20-Bit
Frequency
Register
f
p
20
19*
f
c
Phase
Detector
PD_U
PD_D
M(8:0)
Direct
A(3:0)
Control
R(5:0)
F
R
LD
6
6
C ext
R Counter
* prescaler bypass not available in Direct mode
Document No. 70-0236-04
│
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©2007-2010 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 12
PE97042
Product Specification
Figure 2. Pin Configurations (Top View)
GND
GND
GND
ENH
V
DD
LD
R
3
R
2
R
1
R
0
F
R
Figure 3. Package Type
44-lead CQFJ
6
R
4
R
5
M
0
M
1
V
DD
V
DD
M
2
M
3
S_WR, M
4
DATA, M
5
GND
5
4
3
2
1
44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
C
EXT
V
DD
PD_U
PD_D
GND
N/C
V
DD
D
OUT
V
DD
N/C
GND
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
CLOCK, M
6
D
MODE
M
7
M
8
A
0
E_WR, A
1
A
2
A
3
F
IN
V
DD
F
IN
Table 1. Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
M
4
DATA
16
M
5
Direct
Input
Direct
Serial
Input
Input
Pin Name
V
DD
R
0
R
1
R
2
R
3
GND
R
4
R
5
M
0
M
1
V
DD
V
DD
M
2
M
3
S_WR
Interface Mode
Both
Direct
Direct
Direct
Direct
Both
Direct
Direct
Direct
Direct
Both
Both
Direct
Direct
Serial
Type
(Note 1)
Input
Input
Input
Input
(Note 1)
Input
Input
Input
Input
(Note 1)
(Note 1)
Input
Input
Input
Description
Power supply input. Input may range from 2.85 V to 3.45 V. Bypassing
recommended.
R Counter bit0
R Counter bit1
R Counter bit2
R Counter bit3
Ground
R Counter bit4
R Counter bit5 (MSB)
M Counter bit0
M Counter bit1
Same as pin 1
Same as pin 1
M Counter bit2
M Counter bit3
Frequency register load enable input. Buffered data is transferred to the frequency
register on S_WR rising edge.
M Counter bit4
Binary serial data input. Data is entered LSB first, and is clocked serially into the
20-bit frequency control register (E_WR “low”) or the 8-bit enhancement register
(E_WR “high”) on the rising edge of CLOCK.
M Counter bit5
©2007-2010 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 12
Document No. 70-0236-04
│
UltraCMOS™ RFIC Solutions
PE97042
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
17
Pin Name
GND
CLOCK
Interface Mode
Both
Serial
Direct
Direct
Direct
Direct
Both
Both
Serial
Direct
Direct
Direct
Both
Both
Both
Type
Ground
Input
Input
Input
Input
Input
Input
(Note 1)
Input
Input
Input
Input
Input
Description
Clock input. Data is clocked serially into either the 20-bit primary register (E_WR
“low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of
CLOCK.
M Counter bit6
M Counter bit7
M Counter bit8 (MSB)
A Counter bit0
Selects direct interface mode (D
MODE
=1) or serial interface mode (D
MODE
=0)
Same as pin 1
Enhancement register write enable. While E_WR is “high”, DATA can be serially
clocked into the enhancement register on the rising edge of CLOCK.
A Counter bit1.
A Counter bit2
A Counter bit3 (MSB)
RF prescaler input from the VCO. 3.5 GHz maximum frequency.
F͞
IN
̅
pin requires a 22 pF capacitor in series with a 51 ohm resistor to ground
Ground.
No connect.
18
M
6
19
20
21
22
23
M
7
M
8
A
0
D
MODE
V
DD
E_WR
24
A
1
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Note 1:
Note 2:
A
2
A
3
F
IN
F͞
IN
̅
GND
N/C
V
DD
D
OUT
V
DD
N/C
GND
PD_D̅
PD_U̅
V
DD
C
EXT
GND
GND
F
R
E͞N
͞
H
̅
LD
Both
Both
Both
Both
Both
Both
Both
Both
Both
Serial
Input
Output, OD
Output
(Note 1)
Output
Output
Both
Serial
Both
(Note 1)
Output
(Note 1)
Same as pin 1
Data Out. The Main Counter output, R Counter output, or dual modulus prescaler
select (MSEL) can be routed to D
OUT
through enhancement register programming.
Same as pin 1
No connect.
Ground.
PD_D̅ pulses down when f
p
leads f
c
.
PD_U̅ pulses down when f
c
leads f
p
.
Same as pin 1
Logical “NAND” of PD_U̅ and PD_D̅
,
passed through an on-chip, 2 kΩ series
resistor. Connecting C
EXT
to an external capacitor will low pass filter the input to the
inverting amplifier used for driving LD.
Ground
Ground
Reference frequency input
Enhancement mode. When asserted low (“0”), enhancement register bits are
functional.
Lock detect output, the open-drain logical inversion of C
EXT
. When the loop is
locked, LD is high impedance; otherwise LD is a logic low (“0”).
V
DD
pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level.
All digital input pins have 70 kΩ pull-up resistors to Vdd.
Document No. 70-0236-04
│
www.psemi.com
©2007-2010 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 12
PE97042
Product Specification
Table 2. Absolute Maximum Ratings
Symbol
V
DD
V
I
I
I
I
O
T
stg
Table 4. ESD Ratings
Units
V
V
mA
mA
°C
Parameter/Conditions
Supply voltage
Voltage on any input
DC into any input
DC into any output
Storage temperature
range
Min
-0.3
-0.3
-10
-10
-65
Max
4.0
V
DD
+ 0.3
+10
+10
150
Symbol
V
ESD
Note 1:
Parameter/Conditions
ESD voltage (Human Body
Model) – Note 1
Level
1000
Units
V
Periodically sampled, not 100% tested. Tested per MIL-
STD-883, M3015 C2
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 3. Operating Ratings
Symbol
V
DD
T
A
Parameter/Conditions
Supply voltage
Operating ambient
temperature range
Min
2.85
-40
Max
3.45
85
Units
V
°C
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
Table 5. DC Characteristics:
V
DD
= 3.3 V, -40° C < T
A
< 85° C, unless otherwise specified
Symbol
I
DD
Parameter
Operational supply current;
Prescaler disabled
Prescaler enabled
Conditions
VDD = 3.30 V
Min
Typ
15
45
Max
Units
mA
50
mA
V
Digital Inputs: All except F
R
,
F͞
IN
̅
(all digital inputs have 70 kΩ pull-up resistors)
V
IH
V
IL
I
IH
I
IL
I
IHR
I
ILR
V
OLD
V
OHD
V
OLC
V
OHC
V
OLLD
High level input voltage
Low level input voltage
High level input current
Low level input current
High level input current
Low level input current
Output voltage LOW
Output voltage HIGH
Output voltage LOW, C
EXT
Output voltage HIGH, C
EXT
Output voltage LOW, LD
VDD = 2.85 to 3.45 V
VDD = 2.85 to 3.45 V
VIH = VDD = 3.45 V
VIL = 0, VDD = 3.45 V
VIH = VDD = 3.45 V
VIL = 0, VDD = 3.45 V
I
out
= 6 mA
I
out
= -3 mA
I
out
= 100 µA
I
out
= -100 µA
I
out
= 1 mA
V
DD
- 0.4
0.4
V
DD
- 0.4
0.4
-100
0.4
-1
100
0.7 x V
DD
0.3 x V
DD
70
V
µA
µA
µA
µA
V
V
V
V
V
Reference Divider input: F
R
Counter and phase detector outputs: f
c
, f
p
.
Lock detect outputs: C
EXT
, LD
©2007-2010 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 12
Document No. 70-0236-04
│
UltraCMOS™ RFIC Solutions
PE97042
Product Specification
Table 6. AC Characteristics:
V
DD
= 3.3 V, -40° C < T
A
< 85° C, unless otherwise specified
Symbol
f
Clk
t
ClkH
t
ClkL
t
DSU
t
DHLD
t
PW
t
CWR
t
CE
t
WRC
t
EC
t
MDO
Parameter
CLOCK Serial data clock frequency
CLOCK Serial clock HIGH time
CLOCK Serial clock LOW time
DATA set-up time after CLOCK rising edge
DATA hold time after CLOCK rising edge
S_WR pulse width
CLOCK rising edge to S_WR rising edge.
CLOCK falling edge to E_WR transition
S_WR falling edge to CLOCK rising edge.
E_WR transition to CLOCK rising edge
MSEL data out delay after F
IN
rising edge
Conditions
(Note 1)
Min
Typical
Max
10
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Control Interface and Latches (see Figures 1 and 9)
30
30
10
10
30
30
30
30
30
C
L
= 12 pf
External AC coupling
275 MHz
≤
Freq
≤
3200MHz
External AC coupling
3.2 GHz < Freq
≤
3.5 GHz
3.15 V
≤
VDD
≤
3.45 V
8
ns
Main Divider (Including Prescaler) (Note 4)
-5
0
5
5
dBm
dBm
P
Fin
Input level range
Main Divider (Prescaler Bypassed) (Note 4)
F
IN
P
Fin
Reference Divider
F
R
P
Fr
Phase Detector
f
c
Φ
N
Φ
N
Φ
N
Φ
N
Φ
N
Φ
N
Comparison frequency
(Note 3)
50
MHz
SSB Phase Noise (F
in
= 1.9 GHz, f
r
= 20 MHz, f
c
= 20 MHz, LBW = 50 kHz, V
DD
= 3.3 V, Temp = 25° C
)
(Note 4)
Phase Noise
Phase Noise
Phase Noise
Phase Noise
Phase Noise
Phase Noise
100 Hz Offset
1 kHz Offset
10 kHz Offset
100 Hz Offset
1 kHz Offset
10 kHz Offset
-89
-95
-102
-87
-94
-101
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Operating frequency
Reference input power (Note 2)
(Note 3)
Single-ended input
-2
100
10
MHz
dBm
Operating frequency
Input level range
External AC coupling
50
-5
300
5
MHz
dBm
SSB Phase Noise (F
in
= 1.9 GHz, f
r
= 20 MHz, f
c
= 20 MHz, LBW = 50 kHz, V
DD
= 3.0 V, Temp = 25° C
)
(Note 4)
Note 1: Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk
specification.
Note 2: CMOS logic levels can be used to drive reference input if DC coupled. For Sin wave inputs, amplitude needs to be a minimum of 0.5Vp-p.
Note 3: Parameter is guaranteed through characterization only and is not tested.
Note 4: Parameters below are not tested for die sales. These parameters are verified during the element evaluation.
Document No. 70-0236-04
│
www.psemi.com
©2007-2010 Peregrine Semiconductor Corp. All rights reserved.
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