PRELIMINARY
MX53L12801
ROM MultiMediaCard
1.General Description
The MultiMediaCard MX53L12801 is a highly integrated
read only memory (ROM) with serial and random access
capability using an innovative ultra high density cell
design in the memory array. It is accessible via a
dedicated serial interface optimized for fast and reliable
data transmission. This interface allows several cards to
be stacked by connecting their peripheral contacts. The
MX53L12801 is fully compatible to a new consumer
standard, called the MultiMediaCard system standard
defined in the MultiMediaCard system specification [1].
The MultiMediaCard system is a new mass-storage
system based on innovations in semiconductor
technology. It has been developed to provide an
inexpensive, mechanically robust storage medium in
card form for multimedia consumer applications.
MultiMediaCard allows the design of inexpensive players
and drives without moving parts. A low power
consumption and a wide supply voltage range favors
mobile, battery-powered applications such as audio
players, organizers, palmtops, electronic books,
encyclopedia and dictionaries. Using very effective data
compression schemes such as MPEG, the
MultiMediaCard will deliver enough capacity for all kinds
of multimedia data: software/programs, text, music,
speech, images, video etc.
2. FEATURES
• 16 MByte memory capacity
- Payload: 16,777,216 Bytes
• Small card-sized package: 24x32x1.4 mm (WxLxH)
• MultiMediaCard system standard compatibility
- Sequential and block read supported (Command
classes 0, 1 and 2)
- Block size free programmable between 1~2048 byte
in MMC mode, 1~512 byte in SPI mode
- Multiple block mode supported in MMC mode
- CRC protected data communication
-
2.0V to 3.6V
operation voltage range of
communication
-
2.7V to 3.6V
operation voltage range of memory
access
- Damage free powered card insertion and removal
- MMC and SPI mode available
• High speed serial interface with random access in
block or serial mode
- Byte addressable memory
- up to 10 stacked card @ 10MHz @
2.7-3.6V
- up to 30 stacked card @ 5MHz @
2.7-3.6V
- Access time < 30 us @ 10MHz @
2.7-3.6V
, random
byte access
• Low power dissipation
- High speed: < 126 mW @ 10MHz @
3.6V
- Low power: < 13.5 mW @ 100kHz@
2.7V
- Power save: < 0.27 mW@ 0Hz @
2.7V
(in stby state)
P/N: PM0848
1
REV. 1.3, MAR. 04, 2002
MX53L12801
3.OVERVIEW
The following diagram shows an overview of the MX53L12801 internal architecture:
1
2
3
4
5
6
7
VDD
CMD
MODE_SEL
CLK
Interface driver
DAT
CMD
CLK
DAT
VDD
CID[127:0]
RCA[15:0]
CSD[127:0]
reset
Memory core interface
reset
Memory core
Figure 1 : MX53L12801 architecture
All controllers in the MX53L12801 are clocked by the interface signal CLK. The card is controlled by the three line
MultiMediaCard interface containing the signals: CMD, CLK, DAT (see "Chapter 4: Inter-face" for more details). For
the identification of the MX53L12801 in a stack of MultiMediaCards a card identification register (CID) and a relative
card address register (RCA) is foreseen. An additional register contains different types of operation parameters. This
register is called card specific data register (CSD). The communication using the MultiMediaCard lines to access either
the memory field or the registers is defined by the MultiMediaCard standard (see "Chapter 6: Communication").
The card has its own power on detection unit. No additional master reset signal is required to setup the card after power
on. It is protected against shortcut during insertion and removal while the Multi-MediaCard system is powered up (see
"Chapter 9: Power supply").
P/N: PM0848
Power on detection
REV. 1.3, MAR. 04, 2002
MultiMediaCard
interface
controller
2
MX53L12801
4. INTERFACE
In the MX53L12801 all data is transferred over a minimal number of lines:
•
CLK: with each cycle of this signal a one bit transfer on the command and data lines is done. The frequency may vary
between zero and the maximum clock frequency. The MultiMediaCard bus master is free to generate these cycles
without restrictions in the range of 0-20MHz.
•
CMD: is a bidirectional command channel used for card initialization and data transfer commands. The CMD signal has
two operation modes: open drain for initialization mode and push pull for fast command transfer. Commands are sent
from the MultiMediaCard bus master to the MX53L12801 and responses vice versa.
•
DAT: is a data channel with a width of one line. The DAT signal of the MX53L12801 operates in push pull mode.
R
OD
R
DAT
R
CMD
Interface driver
CMD
DAT
CLK
MultiMediaCard
Host
1 2 3 4 5 6 7
MX53L25600
Figure 2: MX53L12801 interface
All MultiMediaCards are connected directly to the lines of the MultiMediaCard bus. The following
table defines the card contacts.
Pin No.
1
2
3
4
5
6
7
Name
NC
CMD
VSS1
VDD
CLK
VSS2
DAT
Type
1
--
I/PP/OD
S
S
I
S
PP
Description
not connected
Command/Response
Supply voltage ground
Supply voltage
Clock
Supply voltage ground
Data output
Table 1: MX53L12801 pad definition
1
S: power supply; I: input; PP: push pull output; OD: open drain output
P/N: PM0848
3
REV. 1.3, MAR. 04, 2002
MX53L12801
Pin 1 is not connected in the MX53L12801
7
DAT
VSS2
CLK
MultiMediaCard interface controller
6
4
VDD
VSS1
CMD
bus-mode
enable
Interface driver
1
2
Figure 3: MX53L12801 I/O-drivers
P/N: PM0848
Memory core interface
REV. 1.3, MAR. 04, 2002
3
5
4
MX53L12801
5 Registers
The MX53L12801 has the following information registers:
Name
CID
RCA
CSD
Width
128
16
128
Type
Mask programmable,
read only for user
Programmed during
initialization, not readable
Read only
Description
Card identification number, card individual number for
identification.
Relative card address, local system address of a card,
dynamically assigned by the host during initialization.
Card specific data, information about the card operation
conditions.
Table 2: MX53L12801 registers
CID and RCA are used for identifying and addressing the MX53L12801. The third register contains the card specific
data record. This record is a set of information fields to define the operation conditions of the MX53L12801.
For the user the CID and the CSD are read only registers. They are read out by special commands (see "Chapter 6.1:
Commands"). The RCA register is a write only register. Unlike CID and CSD, RCA looses its contents after powering
down the card. Its value is reassigned in each initialization cycle. The complete CID and parts of the CSD are
programmed by the content provider via the programming mask (see "chapter 8: Programming mask format").
5.1 Card identification (CID)
The Card IDentification (CID) register is 128 bits wide. It contains the card identification information used during the
card identification phase (MultiMediaCard protocol). Every individual flash or I/O card shall have an unique
identification number. Every type of MultiMediaCard ROM cards (defined by content) shall have an unique
identification number.
The structure of the CID register is defined in the following paragraphs:
Name
Manufacturer ID
OEM/Application ID
Product name
Product revision
Product serial number
Manufacturing date
CRC7 checksum
not used, always '1'’
Field
MID
OID
PNM
PRV
PSN
MDT
CRC
-
Width
8
16
48
8
32
8
7
1
CID-slice
[127:120]
[119:104]
[103:56]
[55:48]
[47:16]
[15:8]
[7:1]
[0:0]
Value
0x07
"ROM016"
0x00CXXXXX
Table 3: The CID fields
P/N: PM0848
5
REV. 1.3, MAR. 04, 2002
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