PD - 97309A
IRFP4410ZPbF
HEXFET
®
Power MOSFET
Applications
l
High Efficiency Synchronous Rectification in SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
l
Hard Switched and High Frequency Circuits
Benefits
l
Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l
Fully Characterized Capacitance and Avalanche
SOA
l
Enhanced body diode dV/dt and dI/dt Capability
l
Lead-Free
V
DSS
R
DS(on)
typ.
m ax.
I
D (Silicon Lim ited)
D
100V
7.2m
:
9.0m
:
97A
D
D
S
G
S
G
TO-247AC
G
D
S
Gate
Drain
Source
Absolute Maxim um Ratings
Symbol
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
P
D
@T
C
= 25°C
V
GS
dv/dt
T
J
T
STG
Parameter
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Pulsed Drain Current
Max.
97
69
390
230
1.5
± 20
16
-55 to + 175
300
10lb in (1.1N m)
Units
A
W
W/°C
V
V/ns
°C
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
e
x
x
Avalanche Characteristics
E
AS (T hermally limited)
I
AR
E
AR
Single Pulse Avalanche Energy
Avalanche Current
Ã
d
242
See Fig. 14, 15, 22a, 22b,
mJ
A
mJ
Repetitive Avalanche Energy
f
Thermal Resistance
Symbol
R
π
JC
R
π
CS
R
π
JA
Junction-to-Case
j
Parameter
Typ.
–––
0.24
–––
Max.
0.65
–––
40
Units
°C/W
Case-to-Sink, Flat Greased Surface
Junction-to-Ambient
j
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1
03/07/08
IRFP4410ZPbF
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
∆V
(BR)DSS
/∆T
J
R
DS(on)
V
GS(th)
I
DSS
I
GSS
R
G
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
Min. Typ. Max. Units
100
–––
–––
2.0
–––
–––
–––
–––
–––
–––
0.12
7.2
–––
–––
–––
–––
–––
0.70
–––
–––
9.0
4.0
20
250
100
-100
–––
Conditions
V V
GS
= 0V, I
D
= 250µA
V/°C Reference to 25°C, I
D
= 5mAc
mΩ V
GS
= 10V, I
D
= 58A
f
V V
DS
= V
GS
, I
D
= 150µA
µA V
DS
= 100V, V
GS
= 0V
V
DS
= 80V, V
GS
= 0V, T
J
= 125°C
nA V
GS
= 20V
V
GS
= -20V
Ω
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
gfs
Q
g
Q
gs
Q
gd
Q
sync
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
C
oss
eff. (ER)
C
oss
eff. (TR)
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Q
g
- Q
gd
)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Min. Typ. Max. Units
–––
83
19
27
56
16
52
43
57
4820
340
170
420
690
–––
120
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
S
nC
Conditions
V
DS
= 10V, I
D
= 58A
I
D
= 58A
V
DS
=50V
V
GS
= 10V
f
I
D
= 58A, V
DS
=0V, V
GS
= 10V
f
V
DD
= 65V
I
D
= 58A
R
G
=2.7Ω
V
GS
= 10V
f
V
GS
= 0V
V
DS
= 50V
ƒ = 1.0MHz, See Fig.5
V
GS
= 0V, V
DS
= 0V to 80V
h,
See Fig.11
V
GS
= 0V, V
DS
= 0V to 80V
g
140
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Effective Output Capacitance (Energy Related)
h
–––
–––
Effective Output Capacitance (Time Related)g
ns
pF
Diode Characteristics
Symbol
I
S
I
SM
V
SD
t
rr
Q
rr
I
RRM
t
on
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
c
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
Forward Turn-On Time
Min. Typ. Max. Units
–––
–––
–––
–––
97
390
A
A
Conditions
MOSFET symbol
showing the
integral reverse
G
S
D
––– –––
1.3
V
–––
38
57
ns
–––
46
69
–––
53
80
nC
T
J
= 125°C
–––
82
120
–––
2.5
–––
A T
J
= 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
p-n junction diode.
T
J
= 25°C, I
S
= 58A, V
GS
= 0V
f
T
J
= 25°C
V
R
= 85V,
T
J
= 125°C
I
F
= 58A
di/dt = 100A/µs
f
T
J
= 25°C
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.143mH
R
G
= 25Ω, I
AS
= 58A, V
GS
=10V. Part not recommended for use
above this value.
I
SD
≤
58A, di/dt
≤
610A/µs, V
DD
≤
V
(BR)DSS
, T
J
≤
175°C.
Pulse width
≤
400µs; duty cycle
≤
2%.
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom-
mended footprint and soldering techniques refer to application note #AN-994.
R
θ
is measured at T
J
approximately 90°C.
2
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IRFP4410ZPbF
1000
TOP
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
1000
TOP
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
ID, Drain-to-Source Current (A)
100
BOTTOM
ID, Drain-to-Source Current (A)
100
BOTTOM
4.5V
4.5V
10
10
≤
60µs PULSE WIDTH
Tj = 25°C
1
0.1
1
10
100
V DS, Drain-to-Source Voltage (V)
≤
60µs PULSE WIDTH
Tj = 175°C
1
0.1
1
10
100
V DS, Drain-to-Source Voltage (V)
Fig 1.
Typical Output Characteristics
1000
RDS(on) , Drain-to-Source On Resistance
(Normalized)
Fig 2.
Typical Output Characteristics
2.5
ID = 58A
VGS = 10V
2.0
ID, Drain-to-Source Current (A)
VDS = 50V
≤60µs
PULSE WIDTH
100
10
T J = 175°C
1
T J = 25°C
1.5
1.0
0.1
2
3
4
5
6
7
0.5
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
Fig 3.
Typical Transfer Characteristics
100000
VGS = 0V,
f = 1 MHZ
Ciss = C gs + Cgd, C ds SHORTED
Crss = C gd
Coss = Cds + Cgd
Fig 4.
Normalized On-Resistance vs. Temperature
12.0
ID= 58A
VGS, Gate-to-Source Voltage (V)
10.0
VDS= 80V
VDS= 40V
VDS= 20V
C, Capacitance (pF)
10000
Ciss
Coss
1000
Crss
8.0
6.0
4.0
2.0
100
1
10
VDS, Drain-to-Source Voltage (V)
100
0.0
0
20
40
60
80
100
QG, Total Gate Charge (nC)
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFP4410ZPbF
1000
1000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µsec
1msec
100
T J = 175°C
10
T J = 25°C
1
VGS = 0V
0.1
0.0
0.5
1.0
1.5
2.0
2.5
VSD, Source-to-Drain Voltage (V)
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
100
10msec
DC
10
Tc = 25°C
Tj = 175°C
Single Pulse
1
0
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 7.
Typical Source-Drain Diode
Forward Voltage
100
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
Fig 8.
Maximum Safe Operating Area
125
Id = 5mA
120
115
110
105
100
95
90
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Temperature ( °C )
80
ID, Drain Current (A)
60
40
20
0
25
50
75
100
125
150
T C , Case Temperature (°C)
Fig 9.
Maximum Drain Current vs.
Case Temperature
2.0
1.8
1.6
1.4
Energy (µJ)
Fig 10.
Drain-to-Source Breakdown Voltage
1000
EAS , Single Pulse Avalanche Energy (mJ)
900
800
700
600
500
400
300
200
100
0
ID
TOP
6.4A
9.4A
BOTTOM 58A
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-10 0
10 20 30 40 50 60 70 80 90 100
VDS, Drain-to-Source Voltage (V)
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 11.
Typical C
OSS
Stored Energy
Fig 12.
Maximum Avalanche Energy vs. DrainCurrent
4
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IRFP4410ZPbF
1
Thermal Response ( Z thJC ) °C/W
D = 0.50
0.20
0.1
0.10
0.05
0.02
0.01
τ
J
R
1
R
1
τ
J
τ
1
τ
2
R
2
R
2
τ
C
τ
τ
2
Ri (°C/W)
τi
(sec)
0.237
0.000178
0.413
0.003772
τ
1
0.01
Ci=
τi/Ri
Ci i/Ri
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
0.01
0.1
0.001
1E-006
1E-005
0.0001
t1 , Rectangular Pulse Duration (sec)
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆
Tj = 150°C and
Tstart =25°C (Single Pulse)
0.01
Avalanche Current (A)
10
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆Τ
j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
tav (sec)
1.0E-03
1.0E-02
1.0E-01
Fig 14.
Typical Avalanche Current vs.Pulsewidth
150
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 58A
100
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
∆T
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
EAR , Avalanche Energy (mJ)
50
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
DT/
Z
thJC
I
av
= 2DT/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Fig 15.
Maximum Avalanche Energy vs. Temperature
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