INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT174
Hex D-type flip-flop with reset;
positive-edge trigger
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06
1998 Jul 08
Philips Semiconductors
Product specification
Hex D-type flip-flop with reset; positive-edge trigger
FEATURES
•
Six edge-triggered D-type flip-flops
•
Asynchronous master reset
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT174 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
74HC/HCT174
The 74HC/HCT174 have six edge-triggered D-type
flip-flops with individual D inputs and Q outputs. The
common clock (CP) and master reset (MR) inputs load and
reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one set-up time prior to the LOW-to-HIGH clock
transition, is transferred to the corresponding output of the
flip-flop.
A LOW level on the MR input forces all outputs LOW,
independently of clock or data inputs.
The device is useful for applications requiring true outputs
only and clock and master reset inputs that are common to
all storage elements.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL
/ t
PLH
PARAMETER
propagation delay
CP to Q
n
MR to Q
n
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+∑ (C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
maximum clock frequency
input capacitance
power dissipation
capacitance per flip-flop
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
17
13
99
3.5
17
18
17
69
3.5
17
ns
ns
MHz
pF
pF
HCT
UNIT
1998 Jul 08
2
Philips Semiconductors
Product specification
Hex D-type flip-flop with reset; positive-edge trigger
ORDERING INFORMATION
TYPE
NUMBER
74HC174N;
74HCT174N
74HC174D;
74HCT174D
74HC174DB;
74HCT174DB
74HC174PW;
74HCT174PW
PACKAGE
NAME
DIP16
SO16
SSOP16
TSSOP16
DESCRIPTION
plastic dual in-line package; 16 leads (300 mil); long body
plastic small outline package; 16 leads; body width 3.9 mm
74HC/HCT174
VERSION
SOT38-1
SOT109-1
SOT338-1
SOT403-1
plastic shrink small outline package; 16 leads; body width 5.3 mm
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
PIN DESCRIPTION
PIN NO.
1
2, 5, 7, 10, 12, 15
3, 4, 6, 11, 13, 14
8
9
16
SYMBOL
MR
Q
0
to Q
5
D
0
to D
5
GND
CP
V
CC
NAME AND FUNCTION
asynchronous master reset (active LOW)
flip-flop outputs
data inputs
ground (0 V)
clock input (LOW-to-HIGH, edge-triggered)
positive supply voltage
Fig.1 Pin configuration.
Fig.2
Fig.3 IEC logic symbol.
1998 Jul 08
3
Philips Semiconductors
Product specification
Hex D-type flip-flop with reset; positive-edge trigger
74HC/HCT174
Fig.4 Functional diagram.
FUNCTION TABLE
INPUTS
OPERATING MODES
MR
reset (clear)
load “1”
load “0”
Note
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
X = don’t care
↑=
LOW-to-HIGH CP transition
L
H
H
CP
X
↑
↑
D
n
X
h
I
Q
n
L
H
L
OUTPUTS
Fig.5 Logic diagram.
1998 Jul 08
4
Philips Semiconductors
Product specification
Hex D-type flip-flop with reset; positive-edge trigger
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL PARAMETER
+25
min.
t
PHL
/ t
PLH
propagation delay
CP to Q
n
propagation delay
MR to Q
n
output transition time
typ.
55
20
16
t
PHL
44
16
13
t
THL
/ t
TLH
19
7
6
t
W
clock pulse width
HIGH or LOW
80
16
14
t
W
master reset pulse
width; LOW
80
16
14
t
rem
removal time
MR to CP
5
5
5
t
su
set-up time
D
n
to CP
hold time
D
n
to CP
maximum clock pulse
frequency
60
12
10
t
h
3
3
3
f
max
6
30
35
17
6
5
12
4
3
−11
−4
−3
6
2
2
−6
−2
−2
30
90
107
−40
to +85
max. min.
165
33
28
150
30
26
75
15
13
100
20
17
100
20
17
5
5
5
75
15
13
3
3
3
5
24
28
max.
205
41
35
190
38
33
95
19
16
120
24
20
120
24
20
5
5
5
90
18
15
3
3
3
4
20
24
ns
ns
ns
ns
−40
to +125
min.
max.
250
50
43
225
45
38
110
22
19
ns
ns
ns
ns
74HC/HCT174
TEST CONDITIONS
UNIT
V
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
MHz
2.0
4.5
6.0
Fig.6
Fig.8
Fig.8
Fig.7
Fig.7
Fig.6
Fig.6
Fig.7
WAVEFORMS
Fig.6
1998 Jul 08
5
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