SRAM
Austin Semiconductor, Inc.
128K x 8 SRAM
RUGGEDIZED PLASTIC
HIGH SPEED SRAM
FEATURES
•
•
•
•
•
•
•
•
Access times of 15, 20 and 25 ns
Fast output enable (t ) for cache applications
AOE
Low active power
Low standby power
Fully static operation, no clock or refresh required
TTL Compatible Inputs and Outputs
Single +5V power supply
Package in Industry-standard 32-pin SOJ
NC
A6
A5
A4
A3
A2
A1
A0
A16
A15
A14
A13
I/O0
I/O1
I/02
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A7
CE
2
WE\
A8
A9
A10
A11
OE\
A12
CE\
1
I/O7
I/O6
I/O5
I/O4
I/O3
AS5C1008
PIN ASSIGNMENT
(Top View)
32-Pin Plastic SOJ (DJ)
OPTIONS
• Timing
15ns access
20ns access
25ns access
• Package
Plastic SOJ*
MARKING
-15
-20
-25
DJ
No. 905
• Operating Temperature Ranges
-Military (-55
o
C to +125
o
C)
-Industrial (-40
o
C to +85
o
C)
XT
IT
PIN FUNCTIONS
A0 - A16
WE\
Address Inputs
Write Enable
Chip Enable
Output Enable
Data Inputs/Outputs
Power
Ground
No Connection
GENERAL DESCRIPTION
The ASI AS5C1008 is a high speed, low power, 128K by
8-bit ruggedized plastic (COTS) CMOS Static RAM. It is fabri-
cated using high performance, CMOS technology. This highly
reliable process coupled with innovative circuit design tech-
niques, yields access times as fast as 15ns (Max) over the
military and industrial temperature ranges.
When Chip Enable (CE\) is HIGH, the device assumes a
standby mode at which the power dissipation can be reduced
down to 125mW (max) at CMOS input levels.
Easy memory expansion is provided by using asserted LOW
CE\ and asserted HIGH CE2, and asserted LOW write enable
(
WE\) controls both writing and reading of the memory.
TheAS5C1008 is pin-compatible with other 128K x 8
SRAM's in the SOJ package.
CE\
1
, CE
2
OE\
I/O
0
- I/O
7
V
CC
V
SS
NC
For more products and information
please visit our web site at
www.austinsemiconductor.com
*For ceramic versions of this product, please see the
MT5C1008 datasheet.
AS5C1008
Rev. 3.5 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
SRAM
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Vcc Supply Relative to GND...................................-0.5V to +7.0V
Voltage on any pin Relative to GND.........-0.5V to Vcc +7.0V
Storage Temperature ............................................-65°C to +150°C
Ambient Temperature with Power Applied........-55
o
C to +125
o
C
Short Circuit Output Current.................................................260
o
C
Power Dissipation...................................................................1.0W
AS5C1008
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
FUNCTIONAL BLOCK DIAGRAM
A0
Address
A16
Decoder
Memory Matrix
I/O0
Data
I/O7
Input Data
Control
Column I/O
CE\
1
CE
2
WE\
OE\
AS5C1008
Rev. 3.5 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
SRAM
Austin Semiconductor, Inc.
AS5C1008
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55
o
C<T
A
<+125
o
C or -40
o
C to +85
o
C; Vcc = 5V+10%)
PARAMETER
Dynamic Operating
Current
TTL Standby Current -
TTL Inputs
CONDITIONS
Vcc=MAX, I
OUT
= 0mA,
CE
1
= V
IL
and CE
2
= V
IH
, f = fmax
Vcc=MAX, V
IN
= V
IH
or V
IL
,
CE\
1
> V
IH
and CE
2
> V
IL
, f = fmax
Vcc=MAX, CE\
1
> Vcc -0.2V, or CE
2
I
SB2
I
LI
I
LO
V
OH
V
OL
V
IH
V
IL
2.2
-0.5
-10
-10
2.4
0.4
Vcc
+0.5
0.8
2.2
10
10
10
mA
µA
µA
V
0.4
2.2
-0.5
Vcc
+0.5
0.8
V
V
V
-15
-20
-25
SYMBOL MIN MAX MIN MAX MIN MAX UNITS
I
CC1
I
SB1
180
150
140
mA
90
75
70
mA
CMOS Standby Current -
< 0.2V, V
IN
> Vcc -0.2V and
CMOS Inputs
V
IN
< 0.2V, f = 0
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
GND < V
IN
< Vcc
GND < V
OUT
< Vcc
Output Disabled
Vcc = MIN, I
OH
= -4.0 mA
Vcc = MIN, I
OL
= 8.0 mA
10
10
-10
-10
2.4
10
10
-10
-10
2.4
10
10
0.4
Vcc
+0.5
-0.5 0.8
PIN DESCRIPTIONS
A0 - A16: Address Inputs
These 17 address inputs select one of the 131,072 8-bit words in
the RAM.
CE\
1
: Chip Enable 1 Input
CE\
1
is asserted LOW to read from or write to the device. If Chip
Enable 1 is deasserted, the device is deselected and is in standby
power mode. The I/O pins will be in the high-impedance state
when the device is deselected.
CE
2
: Chip Enable 2 Input
CE
2
is asserted HIGH to read from or write to the device. If Chip
Enable 2 is deasserted, the device is deselected and is in standby
power mode. The I/O pins will be in the high-impedance state
when the device is deselected.
OE\: Output Enable Input
The Output Enable Input is asserted LOW. If asserted LOW
while CE\
1
is asserted (LOW) and CE
2
is asserted (HIGH) and
WE\ is deasserted (HIGH), data from the SRAM will be present
on the I/O pins. The I/O pins will be in the high-impedance
state when OE\ is deasserted.
WE\: Write Enable Input
The Write Enable input is asserted LOW and controls read and
write operations. When CE\
1
and WE\ are both asserted (LOW)
and CE
2
is asserted (HIGH) input data present on the I/O pins
will be written into the selected memory location.
AS5C1008
Rev. 3.5 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
SRAM
Austin Semiconductor, Inc.
AS5C1008
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(-55
o
C<T
A
<+125
o
C or -40
o
C to +85
o
C; Vcc = 5V+10%)
-15
DESCRIPTION
READ CYCLE
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Enable Access Time
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
WRITE CYCLE
Write Cycle Time
Chip Enable to End of Write
Address Valid to End of Write
Address Set-up Time
Address Hold from End of Write
Write Pulse Width (OE\ > V
IH
)
Data Set-up Time
Data Hold Time
Write Disable to Output in Low-Z
Write Enable to Output in High-Z
SYMBOL
t
RC
t
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
AOE
t
LZOE
t
HZOE
t
WC
t
CW
t
AW
t
AS
t
AH
t
WP
t
DS
t
DH
t
LZWE
t
HZWE
15
12
12
0
0
12
8
0
5
7
0
7
20
15
15
0
0
15
10
0
5
9
3
3
7
7
0
8
25
20
20
0
0
20
15
0
5
10
1
-20
MIN
20
15
15
3
3
8
7
0
20
20
3
3
MAX
MIN
25
-25
MAX
UNIT
ns
25
25
ns
ns
ns
ns
10
10
ns
ns
ns
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN
15
MAX
NOTE:
1. t
LZCE
, t
LZWE
, t
HZCE
, t
LZOE
, and t
HZOE
are simulated values.
AS5C1008
Rev. 3.5 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
SRAM
Austin Semiconductor, Inc.
CAPACITANCE
(T
A
= +25
o
C, f = 1.0 MHz)
PARAMETER
Input Capacitance
Output Capacitance
CONDITION
V
IN
= 0V
V
OUT
= 0V
SYMBOL
C
IN
C
OUT
MAX
6
8
UNIT
pF
pF
AS5C1008
AC TEST CONDITIONS
Input Pulse Levels.......................................................GND to 3.0V
Input Rise and Fall Times..........................................................3ns
Input Timing Reference Levels................................................1.5V
Output Reference Levels..........................................................1.5V
Output Load..................................................................See Figure 1
+5V
480Ω
Q
255Ω
30 pF
Q
255Ω
+5V
480Ω
5 pF
for t
LZCE
, t
HZCE
, t
LZWE
, t
HZWE
, t
LZOE
, and t
HZOE
Fig. 1 OUTPUT LOAD EQUIVALENT
AS5C1008
Rev. 3.5 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
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