PD -
96177
IRFS4127PbF
IRFSL4127PbF
Applications
l
High Efficiency Synchronous Rectification in SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
l
Hard Switched and High Frequency Circuits
Benefits
l
Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l
Fully Characterized Capacitance and Avalanche
SOA
l
Enhanced body diode dV/dt and dI/dt Capability
l
Lead-Free
HEXFET
®
Power MOSFET
D
G
S
V
DSS
R
DS(on)
typ.
max.
I
D
200V
18.6m
:
22m
:
72A
D
D
S
G
G
D
S
D
2
Pak
IRFS4127PbF
TO-262
IRFSL4127PbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
P
D
@T
C
= 25°C
V
GS
dv/dt
T
J
T
STG
Parameter
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
Max.
72
51
300
375
2.5
± 20
57
-55 to + 175
300
10lb in (1.1N m)
250
See Fig. 14, 15, 22a, 22b,
Units
A
W
W/°C
V
V/ns
°C
c
e
x
x
Avalanche Characteristics
E
AS (Thermally limited)
I
AR
E
AR
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
c
d
f
mJ
A
mJ
Thermal Resistance
Symbol
R
θJC
R
θJA
Junction-to-Case
Junction-to-Ambient
www.irf.com
jk
ij
Parameter
Typ.
–––
–––
Max.
0.4
40
Units
°C/W
1
09/16/08
IRFS/SL4127PbF
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
∆V
(BR)DSS
/∆T
J
R
DS(on)
V
GS(th)
I
DSS
I
GSS
R
G(int)
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
Min. Typ. Max. Units
200
–––
–––
3.0
–––
–––
–––
–––
–––
Conditions
–––
0.23
18.6
–––
–––
–––
–––
–––
3.0
–––
V V
GS
= 0V, I
D
= 250µA
––– V/°C Reference to 25°C, I
D
= 5mA
22
mΩ V
GS
= 10V, I
D
= 44A
5.0
V V
DS
= V
GS
, I
D
= 250µA
V
DS
= 200V, V
GS
= 0V
20
µA
250
V
DS
= 200V, V
GS
= 0V, T
J
= 125°C
100
V
GS
= 20V
nA
V
GS
= -20V
-100
f
–––
Ω
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
gfs
Q
g
Q
gs
Q
gd
Q
sync
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
C
oss
eff. (ER)
C
oss
eff. (TR)
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Q
g
- Q
gd
)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Min. Typ. Max. Units
79
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
100
30
31
69
17
18
56
22
5380
410
86
360
590
–––
150
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
S
Conditions
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
g
h
V
DS
= 50V, I
D
= 44A
I
D
= 44A
V
DS
= 100V
nC
V
GS
= 10V
I
D
= 44A, V
DS
=0V, V
GS
= 10V
V
DD
= 130V
I
D
= 44A
ns
R
G
= 2.7Ω
V
GS
= 10V
V
GS
= 0V
V
DS
= 50V
pF ƒ = 1.0MHz (See Fig.5)
V
GS
= 0V, V
DS
= 0V to 160V (See Fig.11)
V
GS
= 0V, V
DS
= 0V to 160V
f
f
h
g
Diode Characteristics
Symbol
I
S
I
SM
V
SD
t
rr
Q
rr
I
RRM
t
on
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Min. Typ. Max. Units
–––
–––
–––
–––
76
300
A
Conditions
MOSFET symbol
showing the
integral reverse
G
D
Ã
Reverse Recovery Charge
Reverse Recovery Current
Forward Turn-On Time
––– –––
1.3
V
––– 136 –––
ns
––– 139 –––
––– 458 –––
nC
T
J
= 125°C
––– 688 –––
–––
8.3
–––
A T
J
= 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
p-n junction diode.
T
J
= 25°C, I
S
= 44A, V
GS
= 0V
T
J
= 25°C
V
R
= 100V,
T
J
= 125°C
I
F
= 44A
di/dt = 100A/µs
T
J
= 25°C
f
S
f
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.26mH
R
G
= 25Ω, I
AS
= 44A, V
GS
=10V. Part not recommended for use
above this value .
I
SD
≤
44A, di/dt
≤
760A/µs, V
DD
≤
V
(BR)DSS
, T
J
≤
175°C.
Pulse width
≤
400µs; duty cycle
≤
2%.
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
R
θ
is measured at T
J
approximately 90°C
R
θJC
value shown is at time zero
2
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IRFS/SL4127PbF
1000
TOP
1000
ID, Drain-to-Source Current (A)
100
ID, Drain-to-Source Current (A)
10
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
TOP
100
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
10
1
4.5V
1
0.1
4.5V
0.01
0.1
1
≤
60µs PULSE WIDTH
Tj = 25°C
0.1
10
100
0.1
1
≤
60µs PULSE WIDTH
Tj = 175°C
10
100
VDS , Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1.
Typical Output Characteristics
VDS = 50V
RDS(on) , Drain-to-Source On Resistance
(Normalized)
1000
3.5
Fig 2.
Typical Output Characteristics
ID = 44A
3.0
ID, Drain-to-Source Current
(Α)
≤
60µs PULSE WIDTH
100
VGS = 10V
TJ = 175°C
10
2.5
2.0
TJ = 25°C
1
1.5
1.0
0.1
3.0
4.0
5.0
6.0
7.0
8.0
0.5
-60 -40 -20 0
20 40 60 80 100 120 140 160 180
VGS, Gate-to-Source Voltage (V)
TJ , Junction Temperature (°C)
Fig 3.
Typical Transfer Characteristics
8000
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Fig 4.
Normalized On-Resistance vs. Temperature
16
VGS, Gate-to-Source Voltage (V)
ID= 44A
12
6000
C, Capacitance (pF)
Ciss
4000
VDS = 160V
VDS = 100V
VDS = 40V
8
2000
Coss
0
1
Crss
10
VDS, Drain-to-Source Voltage (V)
100
4
0
0
20
40
60
80
100
120
QG Total Gate Charge (nC)
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFS/SL4127PbF
1000
1000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µsec
100
TJ = 175°C
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
100
1msec
10
10msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
0.1
1
10
10
TJ = 25°C
1
VGS = 0V
0.1
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
DC
100
1000
VSD , Source-to-Drain Voltage (V)
VDS , Drain-toSource Voltage (V)
V(BR)DSS, Drain-to-Source Breakdown Voltage (V)
Fig 7.
Typical Source-Drain Diode
Forward Voltage
80
Fig 8.
Maximum Safe Operating Area
260
Id = 5mA
ID, Drain Current (A)
60
240
40
220
20
200
0
25
50
75
100
125
150
175
T C , Case Temperature (°C)
180
-60 -40 -20 0 20 40 60 80 100120140160180
TJ , Temperature ( °C )
Fig 9.
Maximum Drain Current vs.
Case Temperature
EAS, Single Pulse Avalanche Energy (mJ)
8.0
Fig 10.
Drain-to-Source Breakdown Voltage
1000
800
6.0
I D
TOP
8.2A
13A
BOTTOM
44A
Energy (µJ)
600
4.0
400
2.0
200
0.0
0
40
80
120
160
200
0
25
50
75
100
125
150
175
VDS, Drain-to-Source Voltage (V)
Starting TJ, Junction Temperature (°C)
Fig 11.
Typical C
OSS
Stored Energy
Fig 12.
Maximum Avalanche Energy Vs. DrainCurrent
4
www.irf.com
IRFS/SL4127PbF
1
Thermal Response ( ZthJC )
D = 0.50
0.1
0.20
0.10
0.05
τ
J
τ
J
τ
1
R
1
R
1
τ
2
R
2
R
2
R
3
R
3
τ
3
R
4
R
4
τ
C
τ
τ
2
τ
3
τ
4
τ
4
0.01
0.02
0.01
SINGLE PULSE
( THERMAL RESPONSE )
τ
1
Ci=
τi/Ri
Ci i/Ri
Ri (°C/W)
0.02
0.083333
0.181667
0.113333
τι
(sec)
0.000019
0.000078
0.001716
0.008764
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
0.001
0.01
0.1
0.001
1E-006
1E-005
t1 , Rectangular Pulse Duration (sec)
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
Duty Cycle = Single Pulse
0.01
10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆Tj
= 150°C and
Tstart =25°C (Single Pulse)
Avalanche Current (A)
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆Τ
j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14.
Typical Avalanche Current vs.Pulsewidth
250
EAR , Avalanche Energy (mJ)
200
TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 44A
150
100
50
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
∆T
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
175
0
25
50
75
100
125
150
Starting TJ , Junction Temperature (°C)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
DT/
Z
thJC
I
av
= 2DT/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Fig 15.
Maximum Avalanche Energy vs. Temperature
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5
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