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AS6UA51216-BI

产品描述1.65V to 3.6V 512K】16 Intelliwatt low power CMOS SRAM with one chip enable
文件大小115KB，共9页
制造商ALSC [Alliance Semiconductor Corporation]
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AS6UA51216-BI概述

1.65V to 3.6V 512K】16 Intelliwatt low power CMOS SRAM with one chip enable

AS6UA51216-BI文档预览

Advance Information
June 2000
AS6UA51216
1.65V to 3.6V 512K×16 Intelliwatt™ low power CMOS SRAM with one chip enable
Features
•
•
•
•
•
•
•
•
AS6UA51216
Intelliwatt™ active power circuitry
Industrial and commercial temperature ranges available
Organization: 524,288 words × 16 bits
2.7V to 3.6V at 55 ns
2.3V to 2.7V at 70 ns
1.65V to 2.3V at 100 ns
Low power consumption: ACTIVE
- 144 mW at 3.6V and 55 ns
- 68 mW at 2.7V and 70 ns
- 28 mW at 2.3 V and 100 ns
• Low power consumption: STANDBY
- 72 µW max at 3.6V
- 41
µ
W max at 2.7V
- 28
µ
W max at 2.3V
• 1.2V data retention
• Equal access and cycle times
• Easy memory expansion with CS, OE inputs
• Smallest footprint packages
- 48-ball FBGA
- 400-mil 44-pin TSOP II
• ESD protection
≥
2000 volts
• Latch-up current
≥
200 mA
Logic block diagram
A0
A1
A2
A3
A4
A6
A7
A8
A12
A13
I/O1–I/O8
I/O9–I/O16
WE
Row Decoder
V
DD
512K × 16
Array
(8,388,608)
V
SS
Pin arrangement (top view)
44-pin 400-mil TSOP II
A4
1
A5
44
A3
2
43
A6
A2
3
42
A7
A1
4
41
OE
5
A0
UB
40
LB
6
39
CS
I/O16
I/O1
7
38
I/O15
I/O2
8
37
I/O14
I/O3
9
36
I/O13
I/O4
10
35
V
CC
V
SS
11
34
V
SS
V
CC
12
33
I/O5
13
32
I/O12
I/O6
I/O11
14
31
I/O7
I/O10
15
30
I/O8
I/O9
16
29
WE
A8
17
28
A18
18
A9
27
A17
A10
19
26
A16
20
25
A11
A15
21
A12
24
A14
22
A13
23
Note: A “MODE” pad is to be placed between pins 33 and 34 and 11 and 12,
shorted. The bonding of this pad to V
CC
or V
SS
configures the device. There should
only be 44+2+2 pads on the chip. Two extra V
CC
to separate out Array from
Peripheral and Two-Mode Pads.
I/O
buffer
Control circuit
Column decoder
A5
A9
A10
A11
A14
A15
A16
A17
A18
UB
OE
LB
CS
48-CSP Ball-Grid-Array Package
A
B
C
D
E
F
G
H
1
LB
I/O9
I/O10
V
SS
V
CC
I/O15
I/O16
A18
2
3
OE
A0
A3
UB
I/O11 A5
I/O12 A17
I/O13 V
SS
I/O14 A14
NC
A12
A8
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CS
I/O2
I/O4
I/O5
I/O6
WE
A11
6
NC
I/O1
I/O3
V
CC
V
SS
I/O7
I/O8
NC
Selection guide
V
CC
Range
Product
AS6UA51216
AS6UA51216
AS6UA51216
Min
(V)
2.7
2.3
1.65
Typ
2
(V)
3.0
2.5
2.0
Max
(V)
3.6
2.7
2.3
Speed
(ns)
55
70
100
Power Dissipation
Operating (I
CC1
)
Max (mA)
2
1
1
Standby (I
SB2
)
Max (
µ
A)
20
15
12
6/27/00
ALLIANCE SEMICONDUCTOR
1
Copyright ©2000 Alliance Semiconductor. All rights reserved.
AS6UA51216
Functional description
The AS6UA51216 is a low-power CMOS 8,388,608-bit Static Random Access Memory (SRAM) device organized as 524,288 words × 16
bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 55/70/100 ns are ideal for low-power applications. Active high and low chip enables
(CS) permit easy memory expansion with multiple-bank memory systems.
When CS is high, or UB and LB are high, the device enters standby mode: the AS6UA51216 is guaranteed not to exceed 72
µ
W power
consumption at 3.6V and 55ns; 41
µ
W at 2.7V and 70 ns; or 28
µ
W at 2.3V and 100 ns. The device also returns data when V
CC
is reduced
to 1.5V for even lower power consumption.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CS) low, and UB and/or LB low. Data on the input pins I/O1–
O16 is written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices should drive I/O
pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE), chip enable (CS), UB and LB low, with write enable (WE) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is
active, or (UB) and (LB), output drivers stay in high-impedance mode.
These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16.
All chip inputs and outputs are CMOS-compatible, and operation is from either a single 1.65V to 3.6V supply. Device is available in the JEDEC
standard 400-mL, TSOP II, and 48-ball FBGA packages.
Absolute maximum ratings
Parameter
Voltage on V
CC
relative to V
SS
Voltage on any I/O pin relative to GND
Power dissipation
Storage temperature (plastic)
Temperature with V
CC
applied
DC output current (low)
Device
Symbol
V
tIN
V
tI/O
P
D
T
stg
T
bias
I
OUT
Min
–0.5
–0.5
–
–65
–55
–
1.0
+150
+125
20
Max
V
CC
+ 0.5
Unit
V
V
W
°
C
°
C
mA
Note: Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specificati on is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CS
H
L
L
L
WE
X
X
H
H
OE
X
X
H
L
LB
X
H
X
L
H
L
L
L
L
X
H
L
Key: X = Don’t care, L = Low, H = High.
UB
X
H
X
H
L
L
H
L
L
Supply
Current
I
SB
I
CC
I
CC
I/O1–I/O8 I/O9–I/O16
High Z
High Z
D
OUT
High Z
D
OUT
D
IN
High Z
High Z
High Z
D
OUT
D
OUT
High Z
D
IN
D
IN
Mode
Standby (I
SB
)
Output disable (I
CC
)
Read (I
CC
)
I
CC
High Z
D
IN
Write (I
CC
)
2
ALLIANCE SEMICONDUCTOR
6/27/00
AS6UA51216
Recommended operating condition (over the operating range)
Parameter
V
OH
Description
I
OH
= –2.1mA
Output HIGH Voltage
I
OH
= –0.5mA
I
OH
= –0.1mA
I
OL
= 2.1mA
V
OL
Output LOW Voltage
I
OL
= 0.5mA
I
OL
= 0.1mA
V
IH
Input HIGH Voltage
Test Conditions
V
CC
= 2.7V
V
CC
= 2.3V
V
CC
= 1.65V
V
CC
= 2.7V
V
CC
= 2.3V
V
CC
= 1.65V
V
CC
= 2.7V
V
CC
= 2.3V
V
CC
= 1.65V
V
CC
= 2.7V
V
IL
I
IX
I
OZ
I
CC
Input LOW Voltage
Input Load Current
Output Load Current
V
CC
Operating Supply
Current
V
CC
= 2.3V
V
CC
= 1.65V
GND < V
IN
< V
CC
GND < V
O
< V
CC;
Outputs High Z
CS = V
IL
, V
IN
= V
IL
or V
IH
, I
OUT
= 0mA,
f=0
,
CS < 0.2V V
IN
< 0.2V
or V
IN
> V
CC
– 0.2V,
f = 1 mS
V
CC
= 3.6V
V
CC
= 2.7V
V
CC
= 2.3V
V
CC
= 3.6V
V
CC
= 2.7V
V
CC
= 2.3V
V
CC
= 3.6V (55/70/100 mS)
2.2
2.0
1.4
–0.5
–0.3
–0.3
–1
–1
Min
2.4
2.0
1.5
0.4
0.4
0.2
V
CC
+ 0.5
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.6
0.4
+1
+1
2
1
1
4
2
2
40/30/20
30/25/15
25/10/12
100
100
100
20
15
12
2
µ
A
µ
A
µ
A
µ
A
µ
A
Max
Unit
V
V
V
V
mA
I
CC1
@
1 MHz
Average V
CC
Operating
Supply Current at 1 MHz
mA
I
CC2
Average V
CC
Operating
Supply Current
CS
≠
V
IL
, V
IN
= V
IL
or
V
CC
= 2.7V (55/70/100 mS)
V
IH
, f = f
Max
V
CC
= 2.3V(55/70/100 mS)
CS > V
IH
or UB = LB
> V
IH
, other inputs =
V
IL
or V
IH
, f = 0
V
CC
= 3.6V
V
CC
= 2.7V
V
CC
= 2.3V
V
CC
= 3.6V
V
CC
= 2.7V
V
CC
= 2.3V
V
CC
= 1.2V
mA
I
SB
CS Power Down Current;
TTL Inputs
I
SB1
CS > V
CC
– 0.2V or
CS Power Down Current; UB = LB > V
CC
– 0.2V
CMOS Inputs
other inputs = 0V –
V
CC
, f = f
Max
Data Retention
CS > V
CC
– 0.1V,
UB = LB = V
CC
– 0.1V
f=0
I
SBDR
Capacitance (f = 1 MHz, T
a
= Room temperature, V
CC
= NOMINAL)
Parameter
Input capacitance
I/O capacitance
Symbol
C
IN
C
I/O
Signals
A, CS, WE, OE, LB, UB
I/O
Test conditions
V
IN
= 0V
V
IN
= V
OUT
= 0V
Max
5
7
Unit
pF
pF
6/27/00
ALLIANCE SEMICONDUCTOR
3
AS6UA51216
Read cycle (over the operating range)
–55
Parameter
Read cycle time
Address access time
Chip enable (CS) access time
Output enable (OE) access
time
Output hold from address
change
CS
o output in low Z
–70
Max
–
55
55
25
–
–
20
–
55
–
20
20
–
55
Min
70
–
–
–
10
10
0
5
–
10
0
0
0
–
Max
–
70
70
35
–
–
20
–
70
–
20
20
–
70
Min
100
–
–
–
15
10
0
5
–
10
0
0
0
–
–100
Max
–
100
100
50
–
–
20
–
100
–
20
20
–
100
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 5
4, 5
4, 5
4, 5
4, 5
5
4, 5
4, 5
4, 5
3
3
Notes
Symbol
t
RC
t
AA
t
ACS
t
OE
t
OH
t
CLZ
t
CHZ
t
OLZ
t
BA
t
BLZ
t
BHZ
t
OHZ
t
PU
t
PD
Min
55
–
–
–
10
10
0
5
–
10
0
0
0
–
CS high to output in high Z
OE low to output in low Z
UB/LB access time
UB/LB low to low Z
UB/LB high to high Z
OE high to output in high Z
Power up time
Power down time
Shaded areas indicate preliminary information.
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
Read waveform 1 (address controlled)
t
RC
Address
t
OH
D
OUT
Previous data valid
t
AA
Data valid
t
OH
Read waveform 2 (CS, OE, UB, LB controlled)
t
RC
Address
t
AA
OE
t
OLZ
CS
t
LZ
LB, UB
t
BLZ
D
OUT
t
BA
Data valid
t
BHZ
t
ACS
t
OHZ
t
HZ
t
OE
t
OH
4
ALLIANCE SEMICONDUCTOR
6/27/00
AS6UA51216
Write cycle (over the operating range)
–55
Parameter
Write cycle time
Chip enable to write end
Address setup to write end
Address setup time
Write pulse width
Address hold from end of write
Data valid to write end
Data hold time
Write enable to output in high Z
Output active from write end
UB/LB low to end of write
–70
Max
–
–
–
–
–
–
–
–
20
–
–
Min
70
60
60
0
55
0
30
0
0
5
55
Max
–
–
–
–
–
–
–
–
20
–
–
Min
100
80
80
0
70
0
40
0
0
5
70
–100
Max
–
–
–
–
–
–
–
–
20
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 5
4, 5
4, 5
12
12
Notes
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
t
BW
Min
55
40
40
0
35
0
25
0
0
5
35
Shaded areas indicate preliminary information.
Write waveform 1 (WE controlled)
t
WC
Address
t
CW
CS
t
BW
LB, UB
t
AS
WE
t
DW
D
IN
D
OUT
Data undefined
t
WZ
Data valid
t
OW
High Z
t
DH
t
AW
t
WP
t
AH
Write waveform 2 (CS controlled)
t
WC
Address
t
AS
CS
t
CW
t
AW
t
BW
LB, UB
t
WP
WE
t
DW
D
IN
D
OUT
t
CLZ
High Z
t
WZ
Data undefined
Data valid
t
OW
High Z
t
DH
t
AH
6/27/00
ALLIANCE SEMICONDUCTOR
5
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描述 1.65V to 3.6V 512K】16 Intelliwatt low power CMOS SRAM with one chip enable 1.65V to 3.6V 512K】16 Intelliwatt low power CMOS SRAM with one chip enable 1.65V to 3.6V 512K】16 Intelliwatt low power CMOS SRAM with one chip enable 1.65V to 3.6V 512K】16 Intelliwatt low power CMOS SRAM with one chip enable 1.65V to 3.6V 512K】16 Intelliwatt low power CMOS SRAM with one chip enable

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