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AS7C1026-20

产品描述5V / 3.3V 64KX16 CMOS SRAM
产品类别存储    存储   
文件大小145KB,共10页
制造商ALSC [Alliance Semiconductor Corporation]
下载文档 详细参数 全文预览

AS7C1026-20概述

5V / 3.3V 64KX16 CMOS SRAM

AS7C1026-20规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称ALSC [Alliance Semiconductor Corporation]
包装说明,
Reach Compliance Codeunknow

AS7C1026-20文档预览

March 2001
®
AS7C1026
AS7C31026
5V/3.3V 64K×16 CMOS SRAM
Features
• AS7C1026 (5V version)
• AS7C31026 (3.3V version)
• Industrial and commercial versions
• Organization: 65,536 words x 16 bits
• Center power and ground pins for low noise
• High speed
- 12/15/20 ns address access time
- 6,7,8 ns output enable access time
• Low power consumption: ACTIVE
- 880 mW (AS7C1026) / max @ 12 ns
- 396 mW (AS7C31026) / max @ 12 ns
• Low power consumption: STANDBY
- 28 mW (AS7C1026) / max CMOS I/O
- 18 mW (AS7C31026) / max CMOS I/O
• 2.0V data retention
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• JEDEC standard packaging
- 44-pin 400 mil SOJ
- 44-pin 400 mil TSOP II
- 48-ball 6 mm × 8 mm CSP mBGA
• ESD protection
2000 volts
• Latch-up current
200 mA
Logic block diagram
A0
A1
A2
A3
A4
A5
A6
A7
I/O0–I/O7
I/O8–I/O15
Pin arrangement
44-Pin SOJ, TSOP II (400 mil)
V
CC
Row decoder
64K × 16
Array
GND
I/O
buffer
Control circuit
Column decoder
A8
A9
A10
A11
A12
A13
A14
A15
WE
UB
OE
LB
CE
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
V
CC
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
V
CC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
48-CSP mini Ball-Grid-Array Package
1
2
3
4
5
A
LB
OE
A
0
A
1
A
2
B I/O8 UB
A3
A4 CE
C I/O9 I/O10 A5
A6 I/O1
D V
SS
I/O11 NC
A7 I/O3
E V
DD
I/O12 NC
NC I/O4
F I/O14 I/O13 A14 A15 I/O5
G I/O15 NC A12 A13 WE
H NC
A8
A9 A10 A11
6
NC
I/O0
I/O2
V
DD
V
SS
I/O6
I/O7
NC
Selection guide
AS7C1026-12
AS7C31026-12
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
Shaded areas indicate preliminary information.
AS7C1026
AS7C31026
AS7C1026-15
AS7C31026-15
15
8
150
100
10
10
AS7C1026-20
AS7C31026-20
20
10
140
90
15
15
Unit
ns
ns
mA
mA
mA
mA
12
6
AS7C1026
AS7C31026
AS7C1026
AS7C31026
160
110
10
10
3/23/01; v.1.0
Alliance Semiconductor
P. 1 of 10
Copyright © Alliance Semiconductor. All rights reserved.
AS7C1026
AS7C31026
®
Functional description
The AS7C1026 and AS7C31026 are high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices
organized as 65,536 words x 16 bits. They are designed for memory applications where fast data access, low power, and simple
interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 12/15/20 ns with output enable access times (t
OE
) of 6,7,8 ns are ideal
for high-performance applications.
When CE is high the devices enter stanby mode. The AS7C1026 is guaranteed not to exceed 28 mW power consumption in
CMOS standby mode. The devices also offer 2.0V data retention.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0–I/O15 is
written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/
O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. the chips drive
I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write
enable is active, output drivers stay in high-impedance mode.
The devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/O0–I/O7, and UB controls the higher bits, I/O8–I/O15.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply (AS7C1026) or 3.3V supply
(AS7C31026). the device is packaged in common industry standard packages. Chip scale BGA packaging, easy to use in
manufacturing, provides the smallest possible footprint. This 48-ball JEDEC-registered package has a ball pitch of 0.75 mm and
external dimensions of 8 mm × 6 mm.
Absolute maximum ratings
Parameter
Voltage on V
CC
relative to GND
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Ambient temperature with VCC applied
DC current into outputs (low)
AS7C1026
AS7C31026
Symbol
V
t1
V
t1
V
t2
P
D
T
stg
T
bias
I
OUT
Min
–0.50
–0.50
–0.50
–65
–55
Max
+7.0
+5.0
V
CC
+0.50
1.0
+150
+125
20
Unit
V
V
V
W
°C
°C
mA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
H
L
L
L
L
L
WE
X
H
H
H
L
L
OE
X
L
L
L
X
X
LB
X
L
H
L
L
L
UB
X
H
L
L
L
H
I/O0–I/O7
High Z
D
OUT
High Z
D
OUT
D
IN
D
IN
I/O8–I/O15
High Z
High Z
D
OUT
D
OUT
D
IN
High Z
Mode
Standby (I
SB
), I
SBI
)
Read I/O0–I/O7 (I
CC
)
Read I/O8–I/O15 (I
CC)
Read I/O0–I/O15 (I
CC
)
Write I/O0–I/O15 (I
CC
)
Write I/O0–I/O7 (I
CC
)
3/23/01; v.1.0
Alliance Semiconductor
P. 2 of 10
AS7C1026
AS7C31026
®
CE
L
L
L
WE
L
H
X
OE
X
H
X
LB
H
X
H
UB
L
X
H
I/O0–I/O7
High Z
High Z
I/O8–I/O15
D
IN
High Z
Mode
Write I/O8–I/O15 (I
CC
)
Output disable (I
CC
)
Key:
H = High, L = Low, X = don’t care.
Recommended operating conditions
Parameter
Supply voltage
Device
AS7C1026
AS7C31026 (–10)
AS7C31026 (12/15/20)
AS7C1026
Input voltage
commercial
industrial
AS7C31026
Symbol
V
CC
V
CC
V
CC
V
IH
V
IH
V
IL
Ambient operating temperature
Min
4.5
3.15
3.0
2.2
2.0
–0.5
0
–40
Typ
5.0
3.3
3.3
Max
5.5
3.6
3.6
V
CC
+ 0.5
V
CC
+ 0.5
0.8
70
85
Unit
V
V
V
V
V
V
°C
°C
T
A
T
A
V
IL
min = –3.0V for pulse width less than t
RC
/2.
DC operating characteristics (over the operating range)
1
-12
Parameter
Input leakage
current
Output leakage
current
Operating power
supply current
Sym
|
I
LI
|
|
I
LO
|
Test conditions
V
CC
= Max
V
IN
= GND to V
CC
V
CC
= Max
CE = V
IH
,
V
OUT
= GND to V
CC
V
CC
= Max, CE
V
IL
outputs open,
f = f
Max
= 1/t
RC
V
CC
= Max, CE
V
IL
,
outputs open,
f = f
Max
= 1/t
RC
V
CC
= Max, CE
V
CC
–0.2V,
V
IN
GND + 0.2V or
V
IN
V
CC
–0.2V, f = 0
I
OL
= 8 mA, V
CC
= Min
I
OH
= –4 mA, V
CC
= Min
AS7C1026
AS7C31026
AS7C1026
AS7C31026
AS7C1026
AS7C31026
Device
Min
Max
1
Min
-15
Max
1
-20
Min
Max Unit
1
µA
2.4
1
160
110
50
35
10
10
0.4
2.4
1
150
100
50
35
10
10
0.4
2.4
1
140
90
50
35
15
15
0.4
µA
mA
mA
mA
I
CC
Standby
power supply
current
I
SB
I
SB1
V
OL
V
OH
mA
V
V
Output
voltage
Shaded areas indicate preliminary information.
Capacitance (f = 1MHz, T
a
= 25
°C,
V
CC
= NOMINAL)
2
Parameter
Input capacitance
I/O capacitance
3/23/01; v.1.0
Symbol
C
IN
C
I/O
Signals
A, CE, WE, OE, LB, UB
I/O
Test conditions
V
IN
= 0V
V
IN
= V
OUT
= 0V
Max Unit
5
7
pF
pF
Alliance Semiconductor
P. 3 of 10
AS7C1026
AS7C31026
®
Read cycle (over the operating range)
3,9
-12
Parameter
Read cycle time
Address access time
Chip enable (CE) access time
Output enable (OE) access time
Output hold from address change
CE Low to output in low Z
CE High to output in high Z
OE Low to output in low Z
Byte select access time
Byte select Low to low Z
Byte select High to high Z
OE High to output in high Z
Power up time
Power down time
Shaded areas indicate preliminary information.
-15
Max
12
12
6
6
6
6
6
12
Min
15
4
0
0
0
0
Max
15
15
7
6
7
6
6
15
Min
20
4
0
0
0
0
-20
Max
20
20
8
8
8
8
8
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4,5
4,5
4, 5
4, 5
4, 5
5
4, 5
4, 5
4, 5
3
3
Notes
Symbol
t
RC
t
AA
t
ACE
t
OE
t
OH
t
CLZ
t
CHZ
t
OLZ
t
BA
t
BLZ
t
BHZ
t
OHZ
t
PU
t
PD
Min
12
4
0
0
0
0
Key to switching waveforms
Rising input
Falling input
Undefined output/don’t care
Read waveform 1 (address controlled)
3,6,7,9
t
RC
Address
Data
OUT
t
OH
Previous data valid
t
AA
Data valid
t
OH
Read waveform 2 (OE, CE, UB, LB controlled)
3,6,8,9
t
RC
Address
t
AA
OE
t
OLZ
CE
t
LZ
LB, UB
t
BLZ
Data
IN
t
BA
Data valid
t
BHZ
t
ACE
t
OHZ
t
HZ
t
OE
t
OH
3/23/01; v.1.0
Alliance Semiconductor
P. 4 of 10
AS7C1026
AS7C31026
®
Write cycle (over the operating range)
11
-12
Parameter
Write cycle time
Chip enable (CE) to write end
Address setup to write end
Address setup time
Write pulse width
Address hold from end of write
Data valid to write end
Data hold time
Write enable to output in high Z
Output active from write end
Byte select low to end of write
Shaded areas indicate preliminary information.
-15
Min
15
12
10
0
10
0
8
0
1
9
Max
6
6
20
13
12
0
12
0
10
0
2
12
-20
Min
Max
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
4, 5
4, 5
Notes
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
t
BW
Min
12
8
9
0
8
0
6
0
1
8
Max
Write waveform 1 (WE controlled)
10,11
t
WC
Address
t
CW
CE
t
BW
LB, UB
t
AS
WE
t
DW
Data
IN
t
WZ
Data
OUT
Data undefined
Data valid
t
OW
high Z
t
WC
Address
t
AS
CE
t
CW
t
AW
t
BW
LB, UB
t
WP
WE
t
DW
Data
IN
t
CLZ
Data
OUT
high Z
t
WZ
Data undefined
high Z
P. 5 of 10
Data valid
t
OW
t
DH
t
WR
t
DH
t
AW
t
WP
t
WR
Write waveform 2 (CE controlled)
10,11
3/23/01; v.1.0
Alliance Semiconductor
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