FeaTures
n
n
n
n
n
n
n
n
n
n
n
LTC4371
Dual Negative Voltage
Ideal Diode-OR Controller
and Monitor
DescripTion
The
LTC
®
4371
is a two-input negative voltage ideal diode-OR
controller that drives external N-channel MOSFETs as a low
dissipation alternative to Schottky diodes in high power –48V
systems. Low power dissipation and voltage loss eliminates
the need for heatsinks and reduces PC board area. Power
sources can be easily ORed together to increase total system
power and reliability.
The LTC4371 tolerates ±300V transients such as those
experienced during lightning-induced surges and input
supply short-circuit events. The internal shunt regulator
and low 350μA quiescent current allow the use of a large
value dropping resistor to protect the supply pin against
high voltage transients, while the high impedance drain
pins can be similarly protected by high value series resis-
tors without compromising diode operation.
The 220ns reverse current turn-off is achieved by a powerful
2A gate driver with low propagation delay, thereby minimizing
peak reverse current under catastrophic fault conditions. Open
MOSFET and fuse faults are indicated at the FAULTB pin, which
is capable of sinking 5mA to drive an LED or opto isolator.
Controls N-Channel MOSFETs to Replace Power
Schottky Diodes
Low 15mV Forward Voltage Minimizes Dissipation
Withstands > ±300V Transients
Fast Turn-Off: <220ns
Shunt Regulated for High Voltage Applications
4.5V Minimum Operation
Low 350μA Quiescent Current
5mA Gate Pull-Up for 60Hz Applications
High Impedance Drain Pins: <10μA Leakage
Open Fuse and MOSFET Monitor
10-Pin (3mm × 3mm) DFN and MSOP Packages
applicaTions
n
n
n
n
–48V Telecom Power
AdvancedTCA Systems
Network Routers and Switches
Computer Systems and Servers
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
RTN
R
Z
30k
C1
2.2 F
FAULTB
GB
SA
SB V
SS
D1
GREEN LED =
MOSFETS GOOD
V
OUT
50A LOAD
R1
33k
–48V/50A Diode-OR
Power Dissipation vs. Load Current
vs Load Current
40
V
Z
LTC4371
DA
R
DA
20k
V
A
–36V TO
–72V
V
B
–36V TO
–72V
DB
R
DB
20k
M1*
M3*
M2*
GA
V
DD
POWER DISSIPATION (W)
30
SCHOTTKY DIODE
(SBRT60U100CT)
20
POWER
SAVED
10
MOSFET
(2–IPT020N10N3)
4371 TA01a
0
M4*
*M1-M4: IPT020N10N3
0
10
20
30
CURRENT (A)
40
50
4371 TA01b
For more information
www.linear.com/LTC4371
1
4371f
LTC4371
absoluTe MaxiMuM raTings
(Notes 1, 2)
Supply Voltage V
DD
.................................... –0.3V to 17V
Input Voltage
DA, DB (Note 3) .................................... –40V to 100V
SA, SB .................................................. –0.3V to 0.3V
DC Currents
V
Z
......................................................................20mA
DA, DB ............................................................... ±1mA
Single Pulse Current (6ms) DA, DB ........................10mA
Output Voltages
GA, GB ................................................... –0.3V to V
DD
FAULTB .................................................. –0.3V to 17V
Operating Ambient Temperature Range
LTC4371C ................................................ 0°C to 70°C
LTC4371I .............................................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MS Package ...................................................... 300°C
pin conFiguraTion
TOP VIEW
DA 1
GA 2
SA 3
V
Z
4
V
DD
5
11
10 DB
9 GB
8 SB
7 FAULTB
6 V
SS
TOP VIEW
DA
GA
SA
V
Z
V
DD
1
2
3
4
5
10
9
8
7
6
DB
GB
SB
FAULTB
V
SS
DD PACKAGE
10-LEAD (3mm
×
3mm) PLASTIC DFN
MS PACKAGE
10-LEAD PLASTIC MSOP
T
JMAX
= 125°C,
θ
JA
= 160°C/W
T
JMAX
= 125°C,
θ
JA
= 43°C/W (NOTE 4)
EXPOSED PAD (PIN 11) PCB V
SS
CONNECTION OPTIONAL
orDer inForMaTion
(http://www.linear.com/product/LTC4371#orderinfo)
LEAD FREE FINISH
LTC4371CDD#PBF
LTC4371IDD#PBF
LTC4371CMS#PBF
LTC4371IMS#PBF
TAPE AND REEL
LTC4371CDD#TRPBF
LTC4371IDD#TRPBF
LTC4371CMS#TRPBF
LTC4371IMS#TRPBF
PART MARKING
LGSD
LGSD
LTGSF
LTGSF
PACKAGE DESCRIPTION
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead Plastic MSOP
10-Lead Plastic MSOP
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/.
Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
2
4371f
For more information
www.linear.com/LTC4371
LTC4371
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C, I
Z
= 50µA, V
DD
= 12.4V, SA = SB = V
SS
unless otherwise noted.
SYMBOL PARAMETER
V
DD
I
DD
Input Supply Range
Input Supply Current
Normal Operation
Gate Fault to V
SS ,
Strong Pull-Up Disabled
Gate Fault to V
SS,
Strong Pull-Up Enabled
Shunt Regulator Voltage
Shunt Regulator Load Regulation
∆V
SD
= ±0.1V
V
Z
= 10.4V, ∆V
SD
= 0.1V, One GATE = V
SS
I
Z
= 50µA, ∆V
SD
= 0.1V, One GATE = V
SS
I
Z
= 50µA
I
Z
= 50µA to 10mA
CONDITIONS
l
l
l
l
l
l
l
elecTrical characTerisTics
MIN
4.5
200
400
4.5
11.8
10.7
1.15
5
V
DD
– 0.2
–3
7
1
TYP
MAX
16
UNITS
V
µA
µA
mA
V
mV
V
V
V
mV
V
mA
mA
A
ns
300
550
7
12.4
11.2
0.5
1.25
15
–5
10
2
450
750
9.5
14
600
11.8
1.35
25
V
DD
+ 0.1
–8
13
3
220
V
Z
∆V
Z
V
Z(PU)
∆V
Z(PU)
V
Z(PU)
∆V
SD
∆V
GATE
I
GATE(UP)
I
GATE(DN)
t
OFF
I
D
R
D
V
BVD
I
S
V
FAULTB
I
FAULTB
V
Z
High Threshold to Enable Strong Gate Pull-Up V
DD
= V
Z
Rising
V
Z
High Threshold Hysteresis
V
Z
Low Threshold to Enable Strong Gate Pull-Up
Source-Drain Forward Servo Voltage
Gate Drive (V
G
– V
S
)
Gate Pull-Up Current
Gate Pull-Down Current
Strong Gate Pull-Down Current
Gate Turn-Off Time in Fault Condition
DA, DB Leakage Current
MOSFET Off
MOSFET Open
DA, DB Resistance
DA, DB Breakdown Voltage
SA, SB Leakage Current
FAULTB Output Low
FAULTB Leakage Current
I
G
= 0µA, –1µA; ∆V
SD
= 100mV
∆V
SD
= 100mV, ∆V
GATE
= 5V
∆V
SD
= –10mV, ∆V
GATE
= 5V
∆V
SD
= –100mV, ∆V
GATE
= 5V
∆V
SD
= 0.1V Step to –0.4V,
C
GATE
= 3.3nF, ∆V
GATE
<1V
V
D
= 80V
V
D
= –40V
∆V
SD
= –50mV to 0.1V
I
D
= 10mA, 6ms
V
S
= 0V
I
FAULTB
= 5mA
V
FAULTB
= 16V
V
Z
Falling
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
10
–10
1
100
150
2
130
200
5
170
±2
225
0.4
±1
µA
µA
MΩ
V
μA
mV
V
μA
∆V
SD(FLT)
Source-Drain Fault Detection Threshold
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
All currents into pins are positive; all voltages are referenced to
V
SS
unless otherwise specified.
Note 3:
An internal clamp limits the DA and DB pins to a minimum of
100V above V
SS
and –40V below V
SS
. This pin can be safely tied to higher
voltages through a resistance that limits the current below 1mA DC or
10mA for a 6ms transient. Driving this pin with current beyond the clamp
may damage the device.
Note 4:
Thermal resistance is specified with exposed pad soldered to a
3-inch by 4.5-inch, four layer FR4 board. If exposed pad is not soldered
θ
JA
= 93°C/W.
For more information
www.linear.com/LTC4371
3
4371f
LTC4371
Typical perForMance characTerisTics
Supply Current
400
12.75
T
A
= 25°C, unless otherwise noted.
Shunt Regulator Load Regulation
–45
Gate Current vs Forward Voltage
vs Forward Voltage Drop
300
I
DD
(uA)
12.63
I
GATE
(µA)
–30
200
V
Z
(V)
12.50
–15
100
12.38
0
0
0
4
8
V
DD
(V)
12
16
4371 G01
12.25
0.01
0.1
1
I
Z
(mA)
10
100
4371 G02
15
0
15
30
∆V
SD
(mV)
45
60
4371 G03
Drain Current vs Drain Voltage
10
7.5
5
2.5
I
D
(µA)
I
D
(nA)
200
V
DD
= 12.4V
400
Drain Current vs Drain Voltage
V
DD
= 12.4V
50
Load Current vs Forward Voltage
vs Forward Voltage Drop
IPT020N10N3 (2)
40
LOAD CURRENT (A)
85°C
25°C
–40°C
80
4371 G04
30
0.1
0
–0.1
–0.2
–40
0
V
D
(V)
40
85°C
25°C
–40°C
20
0
10
–200
–0.50
–0.25
0
0.25
V
D
(V)
0.50
0.75
4371 G05
0
0
10
20
∆V
SD
(mV)
30
40
4371 G06
Turn-Off Time vs Gate
Capacitance
GATE Capacitance
400
V
DD
= 12.4V
∆V
SD
= 0.1V TO –0.4V
∆V
GATE
≤ 1V
250
Turn-Off Time vs Initial Overdrive
Initial Overdrive
V
DD
= 12.4V
∆V
SD
= V
INITIAL
TO –0.4V
250
Turn-Off Time vs Final Overdrive
(T
OFF
vs V
FINAL
, V
INITIAL
= 0.1V)
Final Overdrive
V
DD
= 12.4V
∆V
SD
= 0.1V TO V
FINAL
300
t
OFF
(ns)
t
OFF
(ns)
200
200
200
t
OFF
(ns)
150
150
100
100
100
50
50
0
0
10
20
30
C
GATE
(nF)
40
50
4371 G07
0
0
0.2
0.4
0.6
V
INITIAL
(V)
0.8
1
4371 G08
0
0
–0.2
–0.4
–0.6
V
FINAL
(V)
–0.8
–1
4371 G09
4
4371f
For more information
www.linear.com/LTC4371
LTC4371
pin FuncTions
DA, DB (Pins 1 and 10):
Drain Voltage Kelvin Sense In-
puts. DA and DB connect to the drains of the N-channel
MOSFETs. The voltage sensed by SA – DA and SB – DB
is used to control the gate drive and hence the ∆V
SD
drop
across the MOSFETs, and it is also used for fault detection.
For accurate Kelvin sensing of ∆V
SD
, connect these pins
as closely as possible to the MOSFET drains. An external
resistor protects the DA and DB pins from transients ex-
ceeding 100V. If the LTC4371 is used in a single channel
application, DA and DB may be joined together and operated
in parallel; otherwise connect the unused drain pin to V
SS
.
Exposed Pad (Pin 11 – DD Package Only):
Exposed pad
may be left open or connected to V
SS
.
FAULTB (Pin 7):
Fault Output. Open drain output that pulls
low to indicate that one or both of the external MOSFETs
have failed open. FAULTB can sink up to 5mA to drive an
opto isolator or LED. The maximum allowable pull-up
voltage is 17V. Connect to V
SS
if unused.
GA, GB (Pins 2 and 9):
Gate Drive Outputs. GA and GB
operate between V
SS
and V
DD
to control their associated
MOSFET gates and emulate the behavior of a diode. For
∆V
SD
>15mV, the gate pin drives the MOSFET on, while
∆V
SD
<15mV produces the opposite effect. With a large
positive ∆V
SD
, the gate pin pulls up with a strong 5mA
source, while large negative ∆V
SD
activates a 2A pull-
down with a maximum propagation delay of 220ns. If the
LTC4371 is used in a single channel application, the gate
pins may be joined together and operated in parallel to
realize a two-fold increase in gate drive strength; otherwise
the unused gate pin may be left open.
SA, SB (Pins 3 and 8):
Source Voltage Kelvin Sense In-
puts. SA and SB connect to the sources of the N-channel
MOSFETs. The voltage sensed by SA – DA and SB – DB
is used to control the gate drive and hence the ∆V
SD
drop
across the MOSFETs, and it is also used for fault detection.
For accurate Kelvin sensing of ∆V
SD
, connect these pins as
close as possible to the MOSFET sources. If the LTC4371
is used in a single channel application, SA and SB may be
joined together and operated in parallel; otherwise connect
the unused source pin to V
SS
.
V
DD
(Pin 5):
Positive Supply Voltage Input. Supply V
DD
directly from 4.5V to 16V, or in shunt regulated applica-
tions connect directly or through a buffer transistor biased
by V
Z
. When connected directly to V
Z
, bypass V
DD
with
2.2μF to V
SS
. Maximum gate drive voltage is limited to V
DD
.
V
SS
(Pin 6):
Device Substrate and Negative Supply Volt-
age. V
SS
connects to V
OUT
at the joined sources of the
N-channel MOSFETs.
V
Z
(Pin 4):
Shunt Regulator Supply Input. This pin serves
as a shunt regulator for the V
DD
pin or as a regulator refer-
ence, and operates with a bias of 50μA to 10mA. Bypass
with at least 100nF when used as a reference, and 2.2μF
when connected to the V
DD
pin. If unused, connect V
Z
to
V
SS
. See “Strong Gate Pull-Up” in the Applications Infor-
mation for details on the relationship between the V
Z
pin
voltage and gate pin drive strength.
For more information
www.linear.com/LTC4371
5
4371f
物联网大赛方案集锦
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
