S i 5 3 5 0 B- B
F
ACTORY
- P
ROGRAMMABLE
A
NY
- F
REQUENCY
CMOS
C
L O C K
G
ENERATOR
+ V C X O
Features
www.silabs.com/custom-timing
Generates up to 8 non-integer-related
frequencies from 2.5 kHz to 200 MHz
Exact frequency synthesis at each
output (0 ppm error)
Highly linear VCXO gain (kv)
Glitchless frequency changes
Low output period jitter: < 70 ps pp, typ
Configurable Spread Spectrum
selectable at each output
User-configurable control pins:
Output Enable (OEB_0/1/2)
Power Down (PDN)
Frequency Select (FS_0/1)
Spread Spectrum Enable (SSEN)
Supports static phase offset
Rise/fall time control
Operates from a low-cost, fixed
frequency AT-cut, non-pullable
crystal: 25 or 27 MHz
Separate voltage supply pins provide
level translation:
Core VDD: 2.5 V or 3.3 V
Output VDDO: 1.8 V, 2.5 V, or 3.3 V
Excellent PSRR eliminates external
power supply filtering
Very low power consumption
(25 mA, core, typ)
Available in 2 packages types:
10-MSOP: 3 outputs
20-QFN (4x4 mm): 8 outputs
PCIE Gen 1 compliant
Supports HCSL compatible swing
10-MSOP
20-QFN
Applications
Ordering Information:
See page 20
Residential gateways
Networking/communication
Servers, storage
XO replacement
HDTV, DVD/Blu-ray, set-top box
Audio/video equipment, gaming
Printers, scanners, projectors
Handheld instrumentation
Description
The Si5350B combines a clock generator and VCXO function into a single device. A
flexible architecture enables this user definable custom timing device to generate
any of the specified output frequencies from either the internal PLL or the VCXO.
This allows the Si5350B to replace multiple crystals, crystal oscillators, and VCXOs.
Custom pin-controlled Si5350B devices can be requested using the ClockBuilder
web-based part number utility:
www.silabs.com/ClockBuilder.
Functional Block Diagram
Rev. 1.0 4/15
Copyright © 2015 by Silicon Laboratories
Si5350B-B
Si5350B-B
Table 1. The Complete Si5350/51 Clock Generator Family
Part Number
Si5351A-B-GT
Si5351A-B-GM
Si5351B-B-GM
Si5351C-B-GM
Si5351A-Bxxxxx-GT
Si5351A-Bxxxxx-GM
Si5351B-Bxxxxx-GM
Si5351C-Bxxxxx-GM
Si5350A-Bxxxxx-GT
Si5350A-Bxxxxx-GM
Si5350B-Bxxxxx-GT
Si5350B-Bxxxxx-GM
Si5350C-Bxxxxx-GT
Si5350C-Bxxxxx-GM
I2C or Pin
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C
Pin
Pin
Pin
Pin
Pin
Pin
Frequency Reference
XTAL only
XTAL only
XTAL and/or Voltage
XTAL and/or CLKIN
XTAL only
XTAL only
XTAL and/or Voltage
XTAL and/or CLKIN
XTAL only
XTAL only
XTAL and/or Voltage
XTAL and/or Voltage
XTAL and/or CLKIN
XTAL and/or CLKIN
Programmed?
Blank
Blank
Blank
Blank
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Outputs
3
8
8
8
3
8
8
8
3
8
3
8
3
8
Datasheet
Si5351-B
Si5351-B
Si5351-B
Si5351-B
Si5351-B
Si5351-B
Si5351-B
Si5351-B
Si5350A-B
Si5350A-B
Si5350B-B
Si5350B-B
Si5350C-B
Si5350C-B
Notes:
1.
XTAL = 25/27 MHz, Voltage = 0 to VDD, CLKIN = 10 to 100 MHz. "xxxxx" = unique custom code.
2.
Create custom, factory pre-programmed parts at www.silabs.com/ClockBuilder.
2
Rev. 1.0
Si5350B-B
T
ABLE O F
C
ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.1. Si5350B Replaces Multiple Clocks and XOs 9
2.2. Applying a Reference Clock at XTAL Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.3. HCSL Compatible Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4. Configuring the Si5350B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.1. Crystal Inputs (XA, XB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2. Output Clocks (CLK0–CLK7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3. Programmable Control Pins (P0–P3) Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4. Voltage Control Input (VC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.5. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1. 20-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2. 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.1. 20-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8. Land Pattern: 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.1. 10-pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9. Land Pattern: 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
10.1. 20-Pin QFN Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10.3. 10-Pin MSOP Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.4. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Rev. 1.0
3
Si5350B-B
1. Electrical Specifications
Table 2. Recommended Operating Conditions
Parameter
Ambient Temperature
Core Supply Voltage
Symbol
T
A
V
DD
Test Condition
Min
–40
3.0
2.25
1.71
Output Buffer Voltage
V
DDOx
2.25
3.0
Typ
25
3.3
2.5
1.8
2.5
3.3
Max
85
3.60
2.75
1.89
2.75
3.60
V
Unit
°C
V
V
Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. VDD
and VDDOx can be operated at independent voltages. Power supply sequencing for VDD and VDDOx requires that all
VDDOx be powered up either before or at the same time as VDD.
Table 3. DC Characteristics
(V
DD
= 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85°C)
Parameter
Symbol
Test Condition
Enabled 3 outputs
Min
—
—
—
—
—
—
—
Typ
20
25
—
2.2
—
—
50
Max
30
40
50
5.6
10
30
—
Unit
mA
mA
µA
mA
µA
µA
Core Supply Current*
I
DD
Enabled 8 outputs
Power Down (PDN = V
DD
)
Output Buffer Supply Current
(Per Output)*
Input Current
I
DDOx
I
P0-P3
I
VC
C
L
= 5 pF
Pins P0, P1, P2, P3
V
P0-P3
< 3.6 V
VC
3.3 V VDDO, default high
drive
Output Impedance
Z
OI
*Note:
Output clocks less than or equal to 100 MHz.
4
Rev. 1.0
Si5350B-B
Table 4. AC Characteristics
(V
DD
= 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85°C)
Parameter
VCXO Control Voltage Range
VCXO Gain (configurable)
VCXO Control Voltage Linearity
VCXO Pull Range
(configurable)*
VCXO Modulation Bandwidth
Power-Up Time
Symbol
Vc
kv
KVL
PR
Test Condition
Min
0
Typ
V
DD
/2
—
—
0
10
2
Max
V
DD
150
+5
±240
—
10
Unit
V
ppm/V
%
ppm
kHz
ms
Vc = 10–90% of V
DD
Vc = 10–90% of V
DD
V
DD
= 3.3 V
Vc = 10–90% of V
DD
18
–5
±30
—
TRDY
From V
DD
= V
DDmin
to valid
output clock, C
L
= 5 pF,
f
CLKn
> 1 MHz
From V
DD
= V
DDmin
to valid
output clock, C
L
= 5 pF,
f
CLKn
> 1 MHz
From OEB assertion to valid
clock output, C
L
= 5 pF,
f
CLKn
> 1 MHz
f
CLKn
> 1 MHz
Down spread. Selectable in
0.1% steps.
—
Power-Up Time, PLL Bypass
Mode
TBYP
—
0.5
1
ms
Output Enable Time
Output Frequency Transition
Time
Spread Spectrum Frequency
Deviation
Spread Spectrum Modulation
Rate
T
OE
—
—
10
µs
T
FREQ
SS
DEV
SS
MOD
—
–0.1
30
—
—
31.5
10
–2.5
33
µs
%
kHz
*Note:
Contact Silicon Labs for VCXO operation at 2.5 V.
Table 5. Input Characteristics
(V
DD
= 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Crystal Frequency
VC Input Resistance
P0-P3 Input Low Voltage
P0-P3 Input High Voltage
Symbol
f
XTAL
Test Condition
Min
25
100
Typ
—
—
—
—
Max
27
—
0.3 x V
DD
3.60
Units
MHz
k
V
V
V
IL_P0-3
V
IH_P0-3
–0.1
0.7 x V
DD
Rev. 1.0
5
嵌入式系统
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