September 2004
Preliminary Information
®
AS9C25512M2018L
AS9C25256M2018L
2.5V 512/256K X 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
Features
• True Dual-Port memory cells that allow simulta-
neous access of the same memory location
• Organisation: 524,288/262,144 × 18
[1]
• Fully Synchronous, independent operation on
both ports
• Selectable Pipeline or Flow-Through output
mode
• Fast clock speeds in Pipeline output mode: 250
MHz operation (9Gbps bandwidth)
• Fast clock to data access: 2.8ns for Pipeline out-
put mode
• Asynchronous output enable control
• Fast OE access times: 2.8ns
• Double Cycle Deselect (DCD) for Pipeline Out-
put Mode
• 19/18
[1]
-bit counter with Increment, Hold and
Repeat features on each port
Note:
1. AS9C25512M2018L/AS9C25256M2018L
•
•
•
•
•
•
•
•
Dual Chip enables on both ports for easy
depth expansion
Interrupt and Collision Detection Features
2.5 V power supply for the core
LVTTL compatible, selectable 3.3V or
2.5V power supply for I/Os, addresses,
clock and control signals on each port
Snooze modes for each port for standby
operation
15mA typical standby current in power
down mode
Available in 256-pin Ball Grid Array
(BGA), 144-pin Thin Quad Flatpack
(TQFP) and 208-pin fine pitch Ball Grid
Array (fpBGA)
Supports JTAG features compliant with
IEEE 1149.1
Selection guide
Feature
Minimum cycle time
Maximum Pipeline clock frequency
Maximum Pipeline clock access time
Maximum flow-through clock frequency
Maximum flow-through clock access time
Maximum operating current
Maximum snooze mode current
-250
4
250
2.8
150
6.5
TBD
18
-200
5
200
3.4
133
7.5
350
18
-166
6
166
3.6
100
10
300
18
-133
7.5
133
4.2
83
12
260
18
Units
ns
MHz
ns
MHz
ns
mA
mA
9/24/04; v.1.2
Alliance Semiconductor
P. 1 of 30
Copyright © Alliance Semiconductor. All rights reserved.
AS9C25512M2018L
AS9C25256M2018L
®
Dual port logic block diagram
R/W Control
R/W Control
BE1
A
-BE0
A
CE0
A
CE1
A
R/W
A
REGISTER BANK
D
Q
REGISTER BANK
D
Q
REGISTER BANK
Q
D
REGISTER BANK
Q
D
BE1
B
-BE0
CE0
B
CE1
B
R/W
B
O/P Control
O/P Control
O/P Control
O/P Control
1
1
0
PL/FT
0
PL/FT
PL/FT
A
OE
A
PL/FT
Qout
A
<17:0>
Qout
B
<17:0>
PL/FT
PL/FT
B
OE
B
REGISTER BANK
Q
D
REGISTER BANK
1
True Dual Port
Memory Array
512/256K X 18
D
Q
REGISTER BANK
REGISTER BANK
DQ17
A
-DQ0
A
D
Q
Din
A
<17:0>
Din
B
<17:0>
Q
D
RPT
A
ADS
A
INC
A
A18
[1]A
-A0
A
Address
Decoding
Increment
Logic
Mirror
Register
REGISTER BANK
D
Q
Address
Decoding
REGISTER BANK
Q
D
Address Counter A
CE0
A
OPT
A
CLK
A
CE1
A
R/W
A
PL/FT
A
CLK
A
OPT
A
INT
A
COL
A
CE0
B
Address Counter B
Interrupt/Collision
Detection
Logic/Registers
CE1
B
R/W
B
PL/FT
B
CLK
B
OPT
B
INT
B
COL
B
OPT
B
CLK
B
ZZ
A
Snooze
Logic
Snooze
Logic
ZZ
B
TDI
TDO
TCK
JTAG
TMS
TRST
Note:
1. Address A18 is a NC for AS9C25256M2018L
9/24/04, v.1.2
Alliance Semiconductor
0
1
DQ17
B
-DQ0
B
RPT
B
ADS
B
INC
B
0
Increment
Logic
Mirror
Register
A18
[1]B
-A0
B
P. 2 of 30
AS9C25512M2018L
AS9C25256M2018L
®
General Description
The AS9C25512M2018L/AS9C25256M2018L is a high-speed CMOS 9/4.5-Mbit synchronous Dual-Port Static Random Access Memory
device, organized as 524,288/262,144 × 18 bits. It incorporates a selectable Flow-Through/Pipeline output feature for user flexibility. Clock-
to-data valid time is 2.8ns at 250 MHz for “Pipeline output” mode of operation.
Each port contains a 19/18 bit linear burst counter on the input address register that can loop through the whole address sequence. After
externally loading the counter with the initial address, it can be Incremented or Held for the next cycle. A new address can also be Loaded or
the “Previous Loaded” address can be re-accessed (Repeated) using counter controls (More description to follow). The Registers on control,
data, and address inputs provide minimal setup and hold times.
The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. A particular port can write
to a certain location while another port is reading from the same location, but the validity of read data is not guaranteed. However, the
reading port is informed about the possible collision through its collision alert signal. The result of writing to the same location by more than
one port at the same time is undefined.
The Asynchronous Output Enable input pin allows asynchronous disabling of output buffers at any given time. The Byte Enable inputs
allow individual byte read/write operations (refer Byte Control Truth Table). An automatic power down feature, controlled by CE0 and CE1,
permits the on-chip circuitry of each port to enter a very low standby power mode.
AS9C25512M2018L/AS9C25256M2018L can support an operating voltage of either 3.3V or 2.5V on either or both ports, which is
controlled by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V. This device is available in 256-pin Ball Grid
Array (BGA), 208-pin fine pitch Ball Grid Array (fpBGA) and 144-pin Thin Quad Flatpack (TQFP)
Address Counter
The AS9C25512M2018L/AS9C25256M2018L carries an internal 19/18 bit address counter for each port which can loop through the entire
memory array. The Address counter features are discussed below:
Load:
Any required external address can be loaded on to the counter. This feature is similar to normal address load in conventional
memories.
Increment:
The address counter has the capability to internally increment the address value, potentially covering the entire memory array.
Once the whole address space is completed, the counter will wrap around. The address counter is not initailized on Power-up, hence a known
location has to be loaded before Increment operation.
Hold:
The value of the counter register can be held for an unlimited number of clock cycles by de-asserting ADS, INC, and RPT inputs.
Repeat:
The previously loaded address (loaded using a valid Load operation) can be re-accessed by asserting RPT input. A separate 19/18
bit register called “Mirror register” is used to hold the last loaded address.This register is not initialized on Power-up, hence a known
location has to be loaded before Repeat operation (Refer Counter control truth table for details).
9/24/04, v.1.2
Alliance Semiconductor
P. 3 of 30
AS9C25512M2018L
AS9C25256M2018L
®
Ball Assignment - 256-ball BGA
AS9C25512M2018L/AS9C25256M2018L
B - 256
Top view
1
A
NC
2
TDI
3
NC
4
A17
A
A18
[1]A
A16
A
5
A14
A
A15
A
A13
A
6
A11
A
A12
A
A10
A
7
A8
A
A9
A
A7
A
8
NC
9
CE1
A
CE0
A
BE0
A
10
OE
A
R/W
A
CLK
A
11
INC
A
RPT
A
ADS
A
12
A5
A
A4
A
A6
A
13
A2
A
A1
A
A3
A
VDD
14
A0
A
VDD
15
NC
16
NC
A
B
INT
A
COL
A
NC
NC
TDO
BE1
A
NC
NC
NC
B
C
DQ9
A
DQ9
B
VSS
OPT
A
NC
NC
DQ8
A
DQ8
B
DQ7
B
DQ6
A
NC
C
D
NC
PL/FT
A
VDDQ
A
VDDQ
A
VDDQ
B
VDDQ
B
VDDQ
A
VDDQ
A
VDDQ
B
VDDQ
B
VDDQ
A
VDD
VDD
NC
VSS
VSS
VSS
VDD
VDD
NC
D
E
DQ10
B
DQ10
A
DQ11
A
NC
NC
NC
VDDQ
B
NC
DQ7
A
NC
E
F
DQ11
B
VDDQ
A
DQ12
A
VDDQ
B
NC
VDDQ
B
VDD
NC
NC
VSS
VSS
VSS
VSS
VDD
VDDQ
B
DQ6
B
VDDQ
A
DQ5
A
VDDQ
A
NC
F
G
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
G
H
NC
DQ12
B
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
DQ5
B
DQ4
A
DQ3
A
DQ2
B
NC
H
J
DQ13
A
DQ14
B
DQ13
B
VDDQ
A
NC
NC
DQ14
A
VDDQ
A
DQ15
B
VDDQ
B
NC
VDDQ
B
ZZ
B
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ZZ
A
VSS
VDDQ
B
DQ4
B
VDDQ
B
NC
DQ3
B
NC
J
K
VSS
VSS
VSS
VSS
VSS
VSS
K
L
DQ15
A
NC
VDD
NC
NC
VSS
VSS
VSS
VSS
VDD
VDDQ
A
DQ2
A
VDDQ
A
DQ1
B
VDD
NC
NC
L
M
DQ16
B
DQ16
A
NC
DQ17
B
DQ17
A
NC
VDD
VDD
NC
VSS
VSS
VSS
VDD
VDD
DQ1
A
DQ0
B
NC
M
N
NC
PL/FT
B
VDDQ
B
VDDQ
B
VDDQ
A
VDDQ
A
VDDQ
B
VDDQ
B
VDDQ
A
VDDQ
A
A16
B
A18
[1]B
A17
B
A13
B
A15
B
A14
B
A10
B
A12
B
A11
B
A7
B
A9
B
A8
B
NC
BE0
B
CE0
B
CE1
B
CLK
B
R/W
B
OE
B
ADS
B
RPT
B
INC
B
A6
B
A4
B
A5
B
NC
N
P
COL
B
INT
B
NC
TMS
A3
B
A1
B
A2
B
NC
DQ0
A
NC
P
R
TRST
BE1
B
NC
OPT
B
A0
B
NC
R
T
TCK
NC
NC
NC
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Note:
1. Address A18 is a NC for AS9C25256M2018L
9/24/04, v.1.2
Alliance Semiconductor
P. 4 of 30
AS9C25512M2018L
AS9C25256M2018L
®
Ball Assignment - 208-ball fpBGA
1
A
DQ9
A
NC
2
INT
A
VSS
3
VSS
4
TDO
5
NC
6
A16
A
A13
A
7
A12
A
A9
A
A10
A
A7
A
8
A8
A
NC
9
NC
10
VDD
11
CLK
A
ADS
A
R/W
A
RPT
A
12
INC
A
A5
A
A6
A
A3
A
13
A4
A
A1
A
A2
A
VDD
14
A0
A
NC
15
OPT
A
16
NC
17
VSS
A
B
COL
A
TDI
A17
A
CE0
A
CE1
A
VDD
VSS
VDDQ
B
DQ8
A
DQ8
B
NC
NC
B
C
VDDQ
A
DQ9
B
VDDQ
B
PL/FT
A
A18
[1]
A14
A
A
NC
VSS
DQ10
A
NC
A15
A
A11
A
BE1
A
BE0
A
VSS
VDD
VSS
C
D
OE
A
NC
VDDQ
A
DQ7
A
NC
VSS
DQ7
B
NC
D
E
DQ11
A
NC
VDDQ
B
DQ10
B
NC
VSS
DQ6
A
VSS
E
F
VDDQ
A
DQ11
B
NC
VSS
DQ6
B
NC
VDDQ
B
NC
F
G
DQ12
A
NC
NC
VDDQ
A
DQ5
A
NC
VSS
G
H
VDD
NC
VDDQ
B
DQ12
B
VSS
ZZ
B
VSS
VDD
DQ5
B
VDDQ
B
VSS
H
J
VDDQ
A
VDD
DQ14
B
NC
VSS
K
DQ13
B
AS9C25512M2018L/AS9C25256M2018L
F - 208
Top view
ZZ
A
VDD
VSS
J
DQ3
B
VDDQ
A
DQ4
B
NC
DQ3
A
NC
VSS
K
L
DQ14
A
VDDQ
B
DQ13
A
NC
DQ15
B
NC
VSS
DQ4
A
L
M
VDDQ
A
NC
VSS
DQ2
B
VDDQ
B
NC
DQ2
A
NC
M
N
VSS
DQ15
A
TRST
A16
B
A13
B
A12
B
A9
B
A10
B
A7
B
A8
B
NC
NC
VDD
CLK
B
ADS
B
R/W
B
RPT
B
INC
B
A5
B
A6
B
A3B
A4
B
A1
B
A2
B
A0
B
DQ1
B
VDDQ
A
NC
DQ1
A
N
P
DQ16
B
DQ16
A
VDDQ
B
COL
B
VSS
NC
DQ17
B
TCK
VSS
P
R
A17
B
CE0
B
CE1
B
VDD
VSS
NC
VDDQ
A
DQ0
B
VDDQ
B
NC
VSS
NC
R
T
NC
DQ17
A
VDDQ
A
TMS
INT
B
PL/FT
B
NC
A18
[1]B
A14
B
A15
B
A11
B
BE1
B
BE0
B
VSS
VSS
T
U
VSS
OE
B
VDD
OPT
B
NC
DQ0
A
U
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Note:
1. Address A18 is a NC for AS9C25256M2018L
9/24/04, v.1.2
Alliance Semiconductor
P. 5 of 30
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