HX711
24-Bit Analog-to-Digital Converter (ADC) for Weigh Scales
DESCRIPTION
Based on Avia Semiconductor’s patented
technology, HX711 is a precision 24-bit analog-
to-digital converter (ADC) designed for weigh
scales and industrial control applications to
interface directly with a bridge sensor.
The input multiplexer selects either Channel A
or B differential input to the low-noise
programmable gain amplifier (PGA). Channel A
can be programmed with a gain of 128 or 64,
corresponding to a full-scale differential input
voltage of ±20mV or ±40mV respectively, when
a 5V supply is connected to AVDD analog power
supply pin. Channel B has a fixed gain of 32. On-
chip power supply regulator eliminates the need
for an external supply regulator to provide analog
power for the ADC and the sensor. Clock input is
flexible. It can be from an external clock source, a
crystal, or the on-chip oscillator that does not
require any external component. On-chip power-
on-reset circuitry simplifies digital interface
initialization.
There is no programming needed for the
internal registers. All controls to the HX711 are
through the pins.
V
AVDD
10uF
Load cell
AVDD
INA+
INA-
Input
MUX
PGA
Gain = 32, 64, 128
Internal
Oscillator
24-bit
Σ∆
ADC
Digital
Interface
Analog Supply Regulator
FEATURES
• Two selectable differential input channels
• On-chip active low noise PGA with selectable gain
of 32, 64 and 128
• On-chip power supply regulator for load-cell and
ADC analog power supply
• On-chip oscillator requiring no external
component with optional external crystal
• On-chip power-on-reset
• Simple digital control and serial interface:
pin-driven controls, no programming needed
• Selectable 10SPS or 80SPS output data rate
• Simultaneous 50 and 60Hz supply rejection
• Current consumption including on-chip analog
power supply regulator:
normal operation < 1.5mA, power down < 1uA
• Operation supply voltage range: 2.6 ~ 5.5V
• Operation temperature range: -40 ~ +85℃
• 16 pin SOP-16 package
APPLICATIONS
• Weigh Scales
• Industrial Process Control
S8550
V
SUP
2.7~5.5V
R2
R1
VFB
BASE
VSUP
DVDD
DOUT
PD_SCK
To/From
MCU
INB+
INB-
VBG
RATE
Bandgap Reference
HX711
0.1uF
AGND
XI
XO
Fig. 1 Typical weigh scale application block diagram
TEL: (592) 252-9530 (P. R. China)
EMAIL:
market@aviaic.com
AVIA SEMICONDUCTOR
HX711
Pin Description
Regulator Power
Regulator Control Output
Analog Power
Regulator Control Input
Analog Ground
Reference Bypass
Ch. A Negative Input
Ch. A Positive Input
VSUP
BASE
AVDD
VFB
AGND
VBG
INNA
INPA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DVDD
RATE
XI
XO
DOUT
INPB
INNB
Digital Power
Output Data Rate Control Input
Crystal I/O and External Clock Input
Crystal I/O
Serial Data Output
PD_SCK
Power Down and Serial Clock Input
Ch. B Positive Input
Ch. B Negative Input
SOP-16L Package
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
VSUP
BASE
AVDD
VFB
AGND
VBG
INA-
INA+
INB-
INB+
PD_SCK
DOUT
XO
XI
RATE
DVDD
Function
Power
Analog Output
Power
Analog Input
Ground
Analog Output
Analog Input
Analog Input
Analog Input
Analog Input
Digital Input
Digital Output
Digital I/O
Digital Input
Digital Input
Power
Description
Regulator supply: 2.7 ~ 5.5V
Regulator control output（NC when not used）
Analog supply: 2.6 ~ 5.5V
Regulator control input（connect to AGND when not used）
Analog Ground
Reference bypass output
Channel A negative input
Channel A positive input
Channel B negative input
Channel B positive input
Power down control (high active) and serial clock input
Serial data output
Crystal I/O (NC when not used）
Crystal I/O or external clock input, 0: use on-chip oscillator
Output data rate control, 0: 10Hz; 1: 80Hz
Digital supply: 2.6 ~ 5.5V
Table 1 Pin Description
AVIA SEMICONDUCTOR
2
HX711
KEY ELECTRICAL CHARACTERISTICS
Parameter
Full scale differential
input range
Common mode input
Internal Oscillator, RATE = 0
Internal Oscillator, RATE =
DVDD
Crystal or external clock,
RATE = 0
Crystal or external clock,
RATE = DVDD
2’s complement
RATE = 0
RATE = DVDD
Input offset drift
Gain = 128
Gain = 64
Input noise
Gain = 128
，
RATE = 0
Gain = 128
，
RATE = DVDD
Temperature drift
Input common mode
rejection
Input offset（Gain = 128）
Gain（Gain = 128）
Gain = 128
，
RATE = 0
800000
400
50
0.2
0.4
50
90
±6
±5
100
100
1.25
1
2.6
2.6
1400
0.3
100
0.2
µA
11.0592
20
5.5
5.5
µA
nV/℃
ppm/℃
dB
dB
V
MHz
V
nV(rms)
mV
Notes
V(inp)-V(inn)
MIN
TYP
±0.5(AVDD/GAIN)
MAX
UNIT
V
AGND+1.2
10
80
f
clk
/1,105,920
f
clk
/138,240
AVDD-1.3
V
Hz
Output data rate
Output data coding
Output settling time
(1)
7FFFFF
HEX
ms
Power supply rejection Gain = 128
，
RATE = 0
Reference bypass
（V
BG
）
Crystal or external clock
frequency
Power supply voltage
Analog supply current
(including regulator)
DVDD
AVDD，VSUP
Normal
Power down
Digital supply current
Normal
Power down
（1）Settling
time refers to the time from power up, reset, input channel change and gain change
to valid stable output data.
Table 2 Key Electrical Characteristics
AVIA SEMICONDUCTOR
3
HX711
Analog Inputs
Channel A differential input is designed to
interface directly with a bridge sensor’s
differential output. It can be programmed with a
gain of 128 or 64. The large gains are needed to
accommodate the small output signal from the
sensor. When 5V supply is used at the AVDD pin,
these gains correspond to a full-scale differential
input voltage of ±20mV or ±40mV respectively.
Channel B differential input has a fixed gain of
32. The full-scale input voltage range is ±80mV,
when 5V supply is used at the AVDD pin.
Output Data Rate and Format
When using the on-chip oscillator, output data
rate is typically 10 (RATE=0) or 80SPS
(RATE=1).
When using external clock or crystal, output
data rate is directly proportional to the clock or
crystal frequency. Using 11.0592MHz clock or
crystal results in an accurate 10 (RTE=0) or
80SPS (RATE=1) output data rate.
The output 24 bits of data is in 2’s complement
format. When input differential signal goes out of
the 24 bit range, the output data will be saturated
at 800000h (MIN) or 7FFFFFh (MAX), until the
input signal comes back to the input range.
Power Supply Options
Digital power supply (DVDD) should be the
same power supply as the MCU power supply.
When using internal analog supply regulator,
the dropout voltage of the regulator depends on
the external transistor used. The output voltage is
equal to V
AVDD
=V
BG
*(R1+R2)/ R1 (Fig. 1). This
voltage should be designed with a minimum of
100mV below VSUP voltage.
If the on-chip analog supply regulator is not
used, the VSUP pin should be connected to either
AVDD or DVDD, depending on which voltage is
higher. Pin VFB should be connected to Ground
and pin BASE becomes NC. The external 0.1uF
bypass capacitor shown on Fig. 1 at the VBG
output pin is then not needed.
Serial Interface
Pin PD_SCK and DOUT are used for data
retrieval, input selection, gain selection and power
down controls.
When output data is not ready for retrieval,
digital output pin DOUT is high. Serial clock
input PD_SCK should be low. When DOUT goes
to low, it indicates data is ready for retrieval. By
applying 25~27 positive clock pulses at the
PD_SCK pin, data is shifted out from the DOUT
output pin. Each PD_SCK pulse shifts out one bit,
starting with the MSB bit first, until all 24 bits are
shifted out. The 25
th
pulse at PD_SCK input will
pull DOUT pin back to high (Fig.2).
Input and gain selection is controlled by the
number of the input PD_SCK pulses (Table 3).
PD_SCK clock pulses should not be less than 25
or more than 27 within one conversion period, to
avoid causing serial communication error.
Input
PD_SCK Pulses
Gain
channel
25
26
27
A
B
A
128
32
64
Clock Source Options
By connecting pin XI to Ground, the on-chip
oscillator is activated. The nominal output data
rate when using the internal oscillator is 10
(RATE=0) or 80SPS (RATE=1).
If accurate output data rate is needed, crystal or
external reference clock can be used. A crystal
can be directly connected across XI and XO pins.
An external clock can be connected to XI pin,
through a 20pF ac coupled capacitor. This
external clock is not required to be a square wave.
It can come directly from the crystal output pin of
the MCU chip, with amplitude as low as 150 mV.
When using a crystal or an external clock, the
internal oscillator is automatically powered down.
AVIA SEMICONDUCTOR
Table 3 Input Channel and Gain Selection
4
HX711
Current Output Data
One conversion period
Next Output Data
DOUT
T
1
PD_SCK
1
MSB
T
2
2
T
3
3
T
4
4
24
LSB
25
Next Conversion：CH.A, Gain:128
PD_SCK
1
2
3
4
24
25
26
Next Conversion：CH.B, Gain:32
PD_SCK
1
2
3
4
24
25
26
27
Next Conversion：CH.B, Gain:64
Fig.2 Data output, input and gain selection timing and control
Symbol
T
1
T
2
T
3
T
4
Note
DOUT falling edge to PD_SCK rising edge
PD_SCK rising edge to DOUT data ready
PD_SCK high time
PD_SCK low time
MIN
0.1
TYP
MAX
0.1
Unit
µs
µs
µs
µs
0.2
0.2
1
1
50
Reset and Power-Down
When chip is powered up, on-chip power on
rest circuitry will reset the chip.
Pin PD_SCK input is used to power down the
HX711. When PD_SCK Input is low, chip is in
normal working mode.
powered down. When PD_SCK returns to low,
chip will reset and enter normal operation mode.
After a reset or power-down event, input
selection is default to Channel A with a gain of
128.
Application Example
Power down:
PD_SCK
60
µ
s
Power down
Normal
Fig.1 is a typical weigh scale application using
HX711. It uses on-chip oscillator (XI=0), 10Hz
output data rate (RATE=0). A Single power
supply
（2.7½5.5V）
comes directly from MCU
power supply. Channel B can be used for battery
level detection. The related circuitry is not shown
on Fig. 1.
Fig.3 Power down control
When PD_SCK pin changes from low to high
and stays at high for longer than 60
µs
, HX711
enters power down mode (Fig.3). When internal
regulator is used for HX711 and the external
transducer, both HX711 and the transducer will be
AVIA SEMICONDUCTOR
5
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