LTC2224
12-Bit, 135Msps ADC
FEATURES
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DESCRIPTIO
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Sample Rate: 135Msps
67.3dB SNR up to 140MHz Input
80dB SFDR up to 150MHz Input
775MHz Full Power Bandwidth S/H
Single 3.3V Supply
Low Power Dissipation: 630mW
CMOS Outputs
Selectable Input Ranges:
±0.5V
or
±1V
No Missing Codes
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Data Ready Output Clock
Pin Compatible Family
135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit)
105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit)
80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit)
48-Pin 7mm
×
7mm QFN Package
The LTC
®
2224 is a 135Msps, sampling 12-bit A/D con-
verter designed for digitizing high frequency, wide dy-
namic range signals. The LTC2224 is perfect for demand-
ing communications applications with AC performance
that includes 67.3dB SNR and 80dB spurious free dy-
namic range for signals up to 150MHz. Ultralow jitter of
0.15ps
RMS
allows undersampling of IF frequencies with
excellent noise performance.
DC specs include
±0.4LSB
INL (typ),
±0.3LSB
DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.5LSB
RMS
.
A separate output power supply allows the CMOS output
swing to range from 0.5V to 3.6V.
The ENC
+
and ENC
–
inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
APPLICATIO S
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Wireless and Wired Broadband Communication
Cable Head-End Systems
Power Amplifier Linearization
Communications Test Equipment
TYPICAL APPLICATIO
REFH
REFL
FLEXIBLE
REFERENCE
3.3V
V
DD
0.5V TO 3.6V
OV
DD
+
ANALOG
INPUT
INPUT
S/H
–
12-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
OUTPUT
DRIVERS
D11
•
•
•
D0
SFDR (dBFS)
OGND
CLOCK/DUTY
CYCLE
CONTROL
2224 TA01
ENCODE
INPUT
U
SFDR vs Input Frequency
95
90
4th OR HIGHER
85
80
75
70
65
60
55
50
0
100
400
500
INPUT FREQUENCY (MHz)
200
300
600
2nd OR 3rd
2224 TA01b
U
U
2224fa
1
LTC2224
ABSOLUTE
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
48 GND
47 V
DD
46 V
DD
45 GND
44 V
CM
43 SENSE
42 MODE
41 OF
40 D11
39 D10
38 OGND
37 OV
DD
OV
DD
= V
DD
(Notes 1, 2)
Supply Voltage (V
DD
) ................................................. 4V
Digital Output Ground Voltage (OGND) ....... –0.3V to 1V
Analog Input Voltage (Note 3) ..... –0.3V to (V
DD
+ 0.3V)
Digital Input Voltage .................... –0.3V to (V
DD
+ 0.3V)
Digital Output Voltage ............... –0.3V to (OV
DD
+ 0.3V)
Power Dissipation ............................................ 1500mW
Operating Temperature Range
LTC2224C ............................................... 0°C to 70°C
LTC2224I .............................................–40°C to 85°C
Storage Temperature Range ..................–65°C to 125°C
A
IN+
1
A
IN–
2
REFHA 3
REFHA 4
REFLB 5
REFLB 6
REFHB 7
REFHB 8
REFLA 9
REFLA 10
V
DD
11
V
DD
12
49
36 D9
35 D8
34 D7
33 OV
DD
32 OGND
31 D6
30 D5
29 D4
28 OV
DD
27 OGND
26 D3
25 D2
UK PACKAGE
48-LEAD (7mm
×
7mm) PLASTIC QFN
EXPOSED PAD IS GND (PIN 49),
MUST BE SOLDERED TO PCB
T
JMAX
= 125°C,
θ
JA
= 29°C/W
ORDER PART
NUMBER
LTC2224CUK
LTC2224IUK
Order Options
Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking:
http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
CO VERTER CHARACTERISTICS
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 4)
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
Offset Drift
Full-Scale Drift
Transition Noise
Internal Reference
External Reference
SENSE = 1V
Differential Analog Input (Note 5)
Differential Analog Input
Single-Ended Analog Input (Note 5)
Single-Ended Analog Input
(Note 6)
External Reference
●
●
CONDITIONS
●
●
●
GND 13
V
DD
14
GND 15
ENC
+
16
ENC
–
17
SHDN 18
OE 19
CLOCKOUT 20
DO 21
OGND 22
OV
DD
23
D1 24
UK PART*
MARKING
LTC2224UK
LTC2224UK
MIN
12
–1
–1
TYP
±0.4
±0.3
±1
±0.3
MAX
1
1
UNITS
Bits
LSB
LSB
LSB
LSB
–35
–2.5
±3
±0.5
±10
±30
±15
0.5
35
2.5
%FS
µV/C
ppm/C
ppm/C
LSB
RMS
2224fa
2
U
mV
W
U
U
W W
W
U
LTC2224
A ALOG I PUT
SYMBOL
V
IN
V
IN, CM
I
IN
I
SENSE
I
MODE
t
AP
t
JITTER
CMRR
The
●
denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T
A
= 25°C. (Note 4)
PARAMETER
Analog Input Range (A
IN+
– A
IN–
)
Analog Input Common Mode (A
IN+
+ A
IN–
)/2
Analog Input Leakage Current
SENSE Input Leakage
MODE Pin Pull-Down Current to GND
Sample and Hold Acquisition Delay Time
Sample and Hold Acquisition Delay Time Jitter
Analog Input Common Mode Rejection Ratio
Full Power Bandwidth
Figure 8 Test Circuit
CONDITIONS
3.1V < V
DD
< 3.5V
Differential Input
Single Ended Input (Note 7)
0 < A
IN+
, A
IN–
< V
DD
0V < SENSE < 1V
●
●
●
●
●
DY A IC ACCURACY
SYMBOL
SNR
PARAMETER
Signal-to-Noise Ratio
The
●
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. A
IN
= –1dBFS. (Note 4)
CONDITIONS
30MHz Input (1V Range)
30MHz Input (2V Range)
70MHz Input (1V Range)
70MHz Input (2V Range)
140MHz Input (1V Range)
140MHz Input (2V Range)
250MHz Input (1V Range)
250MHz Input (2V Range)
SFDR
Spurious Free Dynamic Range
30MHz Input (1V Range)
30MHz Input (2V Range)
70MHz Input (1V Range)
70MHz Input (2V Range)
140MHz Input (1V Range)
140MHz Input (2V Range)
250MHz Input (1V Range)
250MHz Input (2V Range)
SFDR
Spurious Free Dynamic Range
4th Harmonic or Higher
30MHz Input (1V Range)
30MHz Input (2V Range)
70MHz Input (1V Range)
70MHz Input (2V Range)
140MHz Input (1V Range)
140MHz Input (2V Range)
250MHz Input (1V Range)
250MHz Input (2V Range)
S/(N+D)
Signal-to-Noise Plus
Distortion Ratio
30MHz Input (1V Range)
30MHz Input (2V Range)
70MHz Input (1V Range)
70MHz Input (2V Range)
IMD
Intermodulation Distortion
f
IN1
= 138MHz, f
IN2
= 140MHz
●
●
●
U
W U
U
MIN
1
0.5
–1
–1
TYP
±0.5
to
±1
1.6
1.6
MAX
1.9
2.1
1
1
UNITS
V
V
V
µA
µA
µA
ns
ps
RMS
dB
MHz
10
0
0.15
80
775
MIN
66.5
TYP
62.8
67.6
62.8
67.6
62.5
67.3
61.8
65.9
MAX
UNITS
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dBc
72
84
84
84
84
84
84
77
77
90
90
90
90
90
90
90
90
66
62.8
67.4
62.8
67.2
81
2224fa
3
LTC2224
I TER AL REFERE CE CHARACTERISTICS
PARAMETER
V
CM
Output Voltage
V
CM
Output Tempco
V
CM
Line Regulation
V
CM
Output Resistance
3.1V < V
DD
< 3.5V
–1mA < I
OUT
< 1mA
CONDITIONS
I
OUT
= 0
DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL
V
ID
V
ICM
R
IN
C
IN
V
IH
V
IL
I
IN
C
IN
LOGIC OUTPUTS
OV
DD
= 3.3V
C
OZ
I
SOURCE
I
SINK
V
OH
V
OL
OV
DD
= 2.5V
V
OH
V
OL
OV
DD
= 1.8V
V
OH
V
OL
High Level Output Voltage
Low Level Output Voltage
I
O
= –200µA
I
O
= 1.6mA
High Level Output Voltage
Low Level Output Voltage
I
O
= –200µA
I
O
= 1.6mA
Hi-Z Output Capacitance
Output Source Current
Output Sink Current
High Level Output Voltage
Low Level Output Voltage
OE = High (Note 7)
V
OUT
= 0V
V
OUT
= 3.3V
I
O
= –10µA
I
O
= –200µA
I
O
= 10µA
I
O
= 1.6mA
PARAMETER
Differential Input Voltage
Common Mode Input Voltage
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
Input Current
Input Capacitance
(Note 7)
V
DD
= 3.3V
V
DD
= 3.3V
V
IN
= 0V to V
DD
(Note 7)
CONDITIONS
ENCODE INPUTS (ENC
+
, ENC
–
)
The
●
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T
A
= 25°C. (Note 4)
MIN
●
LOGIC INPUTS (OE, SHDN)
●
●
●
4
U
U
U
U
U
(Note 4)
MIN
1.575
TYP
1.600
±25
3
4
MAX
1.625
UNITS
V
ppm/°C
mV/V
Ω
TYP
MAX
UNITS
V
0.2
1.1
1.6
1.6
6
3
2
0.8
–10
3
10
2.5
Internally Set
Externally Set (Note 7)
●
V
V
kΩ
pF
V
V
µA
pF
3
50
50
●
●
pF
mA
mA
V
V
0.4
V
V
V
V
V
V
3.1
3.295
3.29
0.005
0.09
2.49
0.09
1.79
0.09
2224fa
LTC2224
The
●
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 8)
SYMBOL
V
DD
OV
DD
I
VDD
P
DISS
P
SHDN
P
NAP
PARAMETER
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
Power Dissipation
Shutdown Power
Nap Mode Power
SHDN = High, OE = High, No CLK
SHDN = High, OE = Low, No CLK
CONDITIONS
●
●
●
●
POWER REQUIRE E TS
The
●
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 4)
SYMBOL
f
S
t
L
t
H
t
AP
t
OE
t
D
t
C
Pipeline Latency
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3:
When these pin voltages are taken below GND or above V
DD
, they will
be clamped by internal diodes. This product can handle input currents of
greater than 100mA below GND or above V
DD
without latchup.
Note 4:
V
DD
= 3.3V, OV
DD
= 1.8V, f
SAMPLE
= 135MHz, differential
ENC
+
/ENC
–
= 2V
P-P
sine wave, input range = 2V
P-P
with differential drive,
unless otherwise noted.
PARAMETER
Sampling Frequency
ENC Low Time
ENC High Time
Sample-and-Hold Aperture Delay
Output Enable Delay
ENC to DATA Delay
ENC to CLOCKOUT Delay
DATA to CLOCKOUT Skew
(Note 7)
(Note 7)
(Note 7)
(t
C
- t
D
) (Note 7)
●
●
●
●
TI I G CHARACTERISTICS
U W
MIN
3.1
0.5
TYP
3.3
3.3
191
630
2
35
MAX
3.5
3.6
206
680
UNITS
V
V
mA
mW
mW
mW
UW
CONDITIONS
●
MIN
1
3.5
2
3.5
2
●
●
●
●
TYP
3.7
3.7
3.7
3.7
0
5
MAX
135
500
500
500
500
10
3.5
3.5
0.6
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Cycles
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
1.3
1.3
–0.6
2.1
2.1
0
5
Note 5:
Integral nonlinearity is defined as the deviation of a code from a “best
straight line” fit to the transfer curve. The deviation is measured from the
center of the quantization band.
Note 6:
Offset error is the offset voltage measured from –0.5 LSB when the
output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2’s
complement output mode.
Note 7:
Guaranteed by design, not subject to test.
Note 8:
V
DD
= 3.3V, OV
DD
= 1.8V, f
SAMPLE
= 135MHz, differential
ENC
+
/ENC
–
= 2V
P-P
sine wave, input range = 1V
P-P
with differential drive,
output C
LOAD
= 5pF.
2224fa
5
stm32/stm8
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