- Five discrete clock domains, one write clock and four read clocks
- Four separate read ports, read data from four independent Queues
- One single write port, writes to all four independent Queues
simultaneously
- 10-bit wide read ports in single data rate, doubles internally in double
data rate
- 40-bit wide write port, doubles internally in double data rate
- Selectable single or double data rate on read and write ports
- Bus-Matching on the write port x10/x20/x40 (SDR/DDR)
FUNCTIONAL BLOCK DIAGRAMS
Mux Mode
Read Control
Queue 0
Data In
WCLK0
WEN0
WCS0
8,192 x 40
16,384 x40
32,768 x 40
Queue 0
8,192 x 40
16,384 x40
32,768 x 40
Queue 1
8,192 x 40
16,384 x40
32,768 x 40
Queue 2
8,192 x 40
16,384 x40
32,768 x 40
RCLK0
REN0
RCS0
OE0
2
OS[1:0]
D[9:0]
WCLK1
WEN1
WCS1
10
Queue 1
Data In D[19:10]
10
x10,x20,x40
Queue 2
Data In D[29:20]
WCLK2
WEN2
WCS2
10
Data Out
Q[39:0]
Queue 3
Data In D[39:30]
WCLK3
WEN3
WCS3
10
FF0/IR0
PAF0
FF1/IR1
PAF1
FF2/ IR2
PAF2
FF3/IR3
PAF3
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc
(See next pages for Demux and Broadcast modes)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
Read Port
Flag Outputs
Queue 3
EF0/OR0
PAE0
EF1/OR1
PAE1
EF2/OR2
PAE2
EF3/OR3
PAE3
CEF/COR
Write Port
Flag Outputs
1
6157 drw01
DECEMBER 2003
DSC-6157/2
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
List of Contents:
Features ...................................................................................................................................................................................................................... 1,4
DC Electrical Characteristics .......................................................................................................................................................................................... 16
AC Electrical Characteristics ........................................................................................................................................................................................... 17
AC Test Conditions ........................................................................................................................................................................................................ 18
Signal Descriptions ................................................................................................................................................................................................... 30-33
Table 2 — Default Programmable Flag Offsets ................................................................................................................................................................ 20
Table 3 — Status Flags for IDT Standard mode ............................................................................................................................................................. 23
Table 4 — Status Flags for FWFT mode ........................................................................................................................................................................ 23
Table 5 — I/O Voltage Level Associations ....................................................................................................................................................................... 24
Figure 2a. AC Test Load ................................................................................................................................................................................................ 18
Figure 3. Programmable Flag Offset Programming Methods ........................................................................................................................................... 21
Figure 4. Offset Registers Serial Bit Sequence ................................................................................................................................................................ 22
Figure 9. TAP Controller State Diagram ......................................................................................................................................................................... 38
Figure 11. Partial Reset for Mux mode ........................................................................................................................................................................... 42
Figure 12. Partial Reset for Demux mode ...................................................................................................................................................................... 43
Figure 13. Partial Reset for Broadcast mode .................................................................................................................................................................. 44
Figure 14. Write Cycle and Full Flag Timing (Mux mode, IDT Standard mode, SDR to SDR) x10 In to x40 Out ............................................................. 45
Figure 15. Write Cycle and Full Flag Timing (Broadcast Write mode, IDT Standard mode, SDR to SDR) x10 In to x10 Out ............................................ 46
Figure 16. Write Cycle and Full Flag Timing (Demux mode, IDT Standard mode, SDR to SDR) x10 In to x10 Out ......................................................... 47
Figure 17. Write Timing (Mux mode, FWFT mode, SDR to SDR) x10 In to x10 Out ........................................................................................................ 48
Figure 18. Write Timing (Broadcast Write mode, FWFT mode, SDR to SDR) x10 In to x10 Out ....................................................................................... 49
Figure 19. Write Timing (Demux mode, FWFT mode, SDR to SDR) x10 In to x10 Out ................................................................................................... 50
Figure 20. Read Cycle, Empty Flag and First Word Latency (Mux mode, IDT Standard mode, SDR to SDR) x10 In to x40 Out ..................................... 51
Figure 21. Read Timing (Broadcast Write mode, FWFT mode, SDR to SDR) x10 In to x10 Out ...................................................................................... 52
Figure 22. Read Timing (Mux mode, FWFT mode, SDR to SDR) x10 In to x10 Out ....................................................................................................... 53
Figure 23. Read Timing (Demux mode, FWFT mode, SDR to SDR) x20 In to x10 Out .................................................................................................. 53
Figure 24. Read Cycle, Empty Flag and First Word Latency (Demux mode, IDT Standard mode, SDR to SDR) x20 In to x10 Out ................................. 54
Figure 25. Read Cycle, Empty Flag and First Word Latency (Broadcast Write mode, IDT Standard mode, SDR to SDR) x40 In to x10 Out .................... 55
Figure 26. Composite Empty Flag (Mux mode, IDT Standard mode, SDR to SDR) x10 In to x40 Out ............................................................................. 56
Figure 27. Composite Output Ready Flag (Mux mode, FWFT mode, SDR to SDR) x10 In to x40 Out ............................................................................ 56
Figure 28. Composite Full Flag (Demux mode, IDT Standard mode, SDR to SDR) x20 In to x10 Out ............................................................................ 57
Figure 29. Composite Input Ready Flag (Demux mode, FWFT mode, SDR to SDR) x20 In to x10 Out .......................................................................... 57
Figure 30. Echo Read Clock and Read Enable Operation (Mux/Demux/Broadcast mode, IDT Standard mode, DDR to DDR) x10 In to x10 Out ........... 58
Figure 31. Echo RCLK and Echo Read Enable Operation (Mux/Demux/Broadcast mode, FWFT mode, SDR to SDR) .................................................. 59
Figure 32. Echo Read Clock and Read Enable Operation (Mux/Demux/Broadcast mode, IDT Standard mode, SDR to SDR) x10 In to x10 Out ........... 60
Figure 33. Loading of Programmable Flag Registers (IDT Standard and FWFT modes) ................................................................................................ 61
Figure 34. Reading of Programmable Flag Registers (IDT Standard and FWFT modes) ................................................................................................ 61
Figure 35. Synchronous Programmable Almost-Full Flag Timing (see page for details) ................................................................................................... 62
Figure 36. Synchronous Programmable Almost-Empty Flag Timing (see page for details) ............................................................................................... 62
Figure 37. Asynchronous Programmable Almost-Full Flag Timing (see page for details) ................................................................................................ 63
Figure 38. Asynchronous Programmable Almost-Empty Flag Timing (see page for details) ............................................................................................ 63
Figure 39. Power Down Operation ................................................................................................................................................................................ 64
3
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEATURES (CONTINUED)
- Fully independent status flags for every Queue
- Composite Full/Input Ready Flag monitors currently selected Queue
- Dedicated partial reset for every Queue
Up to 200MHz operating frequency, 8Gbps (SDR) and 16Gbps
(DDR)
User selectable Single Data Rate (SDR) or Double Data Rate
(DDR) modes on both the write port(s) and read port(s)
All I/O are LVTTL/ HSTL/ eHSTL user selectable
3.3V tolerant inputs in LVTTL mode
ERCLK and
EREN
Echo outputs on all read ports
Write Chip Select
WCS
input for each write port
Read Chip Select
RCS
input for each read port
User Selectable IDT Standard mode (using
EF
and
FF
flags) or
FWFT mode (using
IR
and
OR
flags)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Composite Full/ Input Ready Flag in Demux and Broadcast
mode
Composite Empty/ Output Ready flag in Mux mode
Independent Programmable Almost Empty and Almost Full flags
per Queue
Dedicated Serial Port for flag programming
Dedicated Partial Reset for each individual Queue
Power Down pin minimizes power consumption
2.5V Supply Voltage
Available in a 324-pin Plastic Ball Grid Array (PBGA)
19mm x 19mm, 1mm Pitch
IEEE 1149.1 compliant JTAG port provides boundary scan
function, or flag programming
Low Power, High Performance CMOS technology
Industrial temperature range (-40°C to +85°C)
°
°
FUNCTIONAL BLOCK DIAGRAMS (CONTINUED)
Demux Mode
WCLK0
WEN0
WCS0
IS[1:0]
2
RCLK0
REN0
RCS0
OE0
10
Queue 0
Write Control
8,192 x 40
16,384 x40
32,768 x 40
Q[9:0]
RCLK1
REN1
RCS1
OE1
Queue 0
Data Out
8,192 x 40
16,384 x40
32,768 x 40
10
Queue 1
Queue 1
Q[19:10] Data Out
RCLK2
REN2
RCS2
OE2
D[39:0]
Data In
x10,x20,x40
8,192 x 40
16,384 x40
32,768 x 40
10
Queue 2
Queue 2
Q[29:20] Data Out
RCLK3
REN3
RCS3
OE3
8,192 x 40
16,384 x40
32,768 x 40
FF0/ IR0
PAF0
FF1/ IR1
PAF1
FF2/ IR2
PAF2
FF3/ IR3
PAF3
CFF/ CIR
Queue 3
10
Queue 3
Data Out
Q[39:30]
EF0/ OR0
PAE0
EF1/ OR1
PAE1
EF2/ OR2
PAE2
EF3/ OR3
PAE3
6157 drw02
4
Read Port
Flag Outputs
Write Port
Flag Outputs
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
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