Si5386 Rev E Data Sheet
12-channel, Any Frequency, Wireless Jitter Attenuating Clock
KEY FEATURES
The Si5386 is a high performance, integer and fractional clock generator for wireless
applications which demand the highest level of integration and phase noise perform-
ance. Based on Silicon Laboratories’ 4th generation DSPLL technology, the Si5386
combines frequency synthesis and jitter attenuation in a highly integrated digital sol-
ution that eliminates the need for external VCXO and loop filter components. A fixed-
frequency crystal that provides frequency stability for free-run and holdover modes is
integrated within the package saving valuable PCB space. This all-digital solution
provides superior performance that is highly immune to external board disturbances
such as power supply noise.
Modern C-RAN remote radio heads and fixed wireless systems require a diverse set
of clocks such as ADC/DAC, RF LOs, eCPRI/CPRI, and Ethernet clocks. The
Si5386 architecture is designed to deliver high-performance JESD204B DCLK and
SYSREF clock pairs and flexible any-rate clocks for non-LTE clocks such as Ether-
net and system reference clocks all from a single IC.
Applications:
• Cloud Radio Access Network RRHs
• Small cells
• Fixed wireless
• Wireless base stations
• Active antenna systems
• Distributed antenna systems
Integrated Reference
• Flexible timing in a single IC
• Generates any combination of output
frequencies from any input frequency
• Input frequency range:
• Differential: 7.68 MHz to 750 MHz
• LVCMOS: 7.68 MHz to 250 MHz
• Output frequency range (Integer):
• Differential: up to 3 GHz
• Output frequency range (fractional):
• Differential: up to 735 MHz
• LVCMOS: up to 250 MHz
• Ultra-low jitter:
• 80 fs typ (12 kHz–20 MHz)
IN_SEL
OSC
IN0
÷INT
DSPLL
IN1
IN2
IN3/FB_IN
÷INT
÷INT
÷INT
÷INT
÷INT
OUT0
OUT0A
0
÷INT
Multi
Synth
Multi
Synth
Multi
Synth
Multi
Synth
SPI/
I
2
C
Multi
Synth
÷INT
OUT1
OUT2
÷INT
OUT3
÷INT
OUT4
0
÷INT
÷INT
OUT5
I2C_SEL
SDA/SDIO
A1/SDO
SCLK
A0/CSb
NVM
LOLb
INTRb
OUT6
÷INT
OUT7
÷INT
OUT8
0
÷INT
Status
Monitors
÷INT
PDNb
RSTb
SYNCb
OEb
OUT9
OUT9A
silabs.com
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Rev. 0.9
Table of Contents
1. Features List
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2. Ordering Guide
3. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Frequency Configuration .
3.2 DSPLL Loop Bandwidth
3.3 Fastlock Feature .
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. 6
. 6
. 6
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6
7
7
7
7
8
3.4 Modes of Operation . . .
3.4.1 Initialization and Reset
3.4.2 Freerun Mode . . .
3.4.3 Lock Acquisition Mode
3.4.4 Locked Mode . . .
3.4.5 Holdover Mode . .
3.5 Inputs (IN0, IN1, IN2, IN3) . . . . . . . . .
3.5.1 Manual Input Switching (IN0, IN1, IN2, IN3) .
3.5.2 Automatic Input Selection (IN0, IN1, IN2, IN3)
3.5.3 Hitless Input Switching . . . . . . . .
3.5.4 Ramped Input Switching . . . . . . .
3.5.5 Glitchless Input Switching . . . . . . .
3.5.6 Input Configuration and Terminations . . .
3.6 Fault Monitoring . . . . . . . .
3.6.1 Input LOS Detection. . . . .
3.6.2 Reference Clock LOS Detection.
3.6.3 OOF Detection . . . . . .
3.6.4 LOL Detection . . . . . . .
3.6.5 Interrupt Pin (INTRb) . . . .
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. 8
. 9
. 9
. 9
. 9
. 9
.10
.11
.11
.11
.12
.13
.14
.14
.14
.14
.15
.15
.15
.16
.16
.16
.16
.16
.16
.17
.17
.17
.17
.18
3.7 Outputs . . . . . . . . . . . . . . . . . . . . .
3.7.1 Output Crosspoint . . . . . . . . . . . . . . .
3.7.2 Output Signal Format . . . . . . . . . . . . . .
3.7.3 Differential Output Terminations . . . . . . . . . . .
3.7.4 LVCMOS Output Terminations . . . . . . . . . . .
3.7.5 Programmable Common Mode Voltage For Differential Outputs
3.7.6 LVCMOS Output Impedance Selection . . . . . . . .
3.7.7 LVCMOS Output Signal Swing . . . . . . . . . . .
3.7.8 LVCMOS Output Polarity . . . . . . . . . . . . .
3.7.9 Output Enable/Disable . . . . . . . . . . . . . .
3.7.10 Output Driver State When Disabled . . . . . . . . .
3.7.11 Synchronous Output Disable Feature . . . . . . . .
3.7.12 Zero Delay Mode . . . . . . . . . . . . . . .
3.7.13 Output Divider (R) Synchronization . . . . . . . . .
3.8 Power Management .
3.10 Serial Interface .
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3.9 In-Circuit Programming .
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Rev. 0.9 | 2
3.11 Custom Factory Preprogrammed Parts .
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.18
3.12 Enabling Features and/or Configuration Settings Unavailable in ClockBuilder Pro for Factory Pre-
programmed Devices . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4. Register Map
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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.20
.20
4.1 Addressing Scheme .
4.2 High-Level Register Map .
5. Electrical Specifications
. . . . . . . . . . . . . . . . . . . . . . . . . . 22
35
6. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . .
7. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8. Typical Operating Characteristics
9. Pin Descriptions
10. Package Outlines
. . . . . . . . . . . . . . . . . . . . . .37
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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.44
.46
10.1 Si5386 9x9 mm 64-LGA Package Diagram
10.2 Si5386 9x9 mm 64-QFN Package Diagram
11. PCB Land Pattern
12. Top Marking
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
13. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
14. Document Change List
14.1 Revision 0.9 .
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. . . . . . . . . . . . . . . . . . . . . . . . . . 51
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.51
silabs.com
| Building a more connected world.
Rev. 0.9 | 3
Si5386 Rev E Data Sheet
Features List
1. Features List
The Si5386 Rev. E features are listed below:
• Flexible timing in a single IC
• Generates any combination of output frequencies from any
input frequency
• Input frequency range:
• Differential: 7.68 MHz to 750 MHz
• LVCMOS: 7.68 MHz to 250 MHz
• Output frequency range (Integer):
• Differential: up to 2.94912 GHz with JESD204B support
• Output frequency range (fractional):
• Differential: up to 735 MHz
• LVCMOS: up to 250 MHz
• Ultra-low jitter: 80 fs typ (12 kHz–20 MHz)
• Programmable jitter attenuation bandwidth from 1 Hz to 4 kHz
• Highly configurable outputs compatible with LVDS, LVPECL,
LVCMOS, CML, and HCSL with programmable signal ampli-
tude from 200 - 3200 mV
•
•
•
•
•
•
•
•
•
Status monitoring (LOS, OOF, LOL)
Pin controlled input switching
DSPLL with special wireless calibration
Optional zero delay mode
Hitless input clock switching: automatic or manual
Automatic free-run and holdover modes
Fastlock feature
Glitchless on the fly output frequency changes
Core voltage:
• VDD: 1.8 V ±5%
• VDDA: 3.3 V ±5%
Independent output clock supply pins: 3.3 V, 2.5 V, or 1.8 V
Output-output skew: 20 ps typ
Serial interface: I2C or SPI
In-circuit programmable with non-volatile OTP memory
ClockBuilder ProTM software simplifies device configuration
Temperature range: –40 to +85 °C
•
•
•
•
•
•
silabs.com
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Rev. 0.9 | 4
Si5386 Rev E Data Sheet
Ordering Guide
2. Ordering Guide
Ordering Part Num-
Reference
ber (OPN)
Si5386
Si5386A-E-GM
1, 2
External Crystal
4/10
0.001 to 2949.12
MHz
0.001 to 2949.12
MHz
Integer and
Fractional
Integer and
Fractional
64-QFN
9×9 mm
64-LGA
9×9 mm
–40 to 85
°C
–40 to 85
°C
Number of In-
put/Output
Clocks
Output Clock Fre-
quency Range
(MHz)
Supported Fre-
quency Synthesis Package
Modes
Tempera-
ture Range
Si5386E-E-GM
1, 2
Internal Crystal
4/10
Notes:
1. Add an R at the end of the OPN to denote tape and reel ordering options.
2. Custom, factory preprogrammed devices are available. Ordering part numbers are assigned by Silicon Labs and the ClockBuilder
Pro software utility. Custom part number format is “Si5386E-Exxxxx-GM” where “xxxxx” is a unique numerical sequence repre-
senting the preprogrammed configuration.
Figure 2.1. Ordering Part Number Fields
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Rev. 0.9 | 5
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