Si5347/46 Rev D Data Sheet
Dual/Quad DSPLL
™
Any-Frequency, Any-Output Jitter
Attenuators
The Si5347 is a high-performance, jitter-attenuating clock multiplier which integrates
four any-frequency DSPLLs for applications that require maximum integration and inde-
pendent timing paths. The Si5346 is a dual DSPLL version in a smaller package. Each
DSPLL has access to any of the four inputs and can provide low jitter clocks on any of
the device outputs. Based on 4
th
generation DSPLL technology, these devices provide
any-frequency conversion with typical jitter performance under 100 fs. Each DSPLL
supports independent free-run, holdover modes of operation, as well as automatic and
hitless input clock switching. The Si5347/46 is programmable via a serial interface with
in-circuit programmable non-volatile memory so that it always powers up in a known
configuration. Programming the Si5347/46 is easy with Silicon Labs'
ClockBuilder Pro
software. Factory pre-programmed devices are also available.
KEY FEATURES
• Four or two independent DSPLLs, any
output frequency from any input frequency
• Ultra-low jitter of 95 fs rms
• Input frequency range:
• External Crystal: 25–54 MHz
• Differential: 8 kHz to 750 MHz
• LVCMOS: 8 kHz to 250 MHz
• Output frequency range:
• Differential: up to 712.5 MHz
• LVCMOS: up to 250 MHz
• Status Monitoring
• Hitless switching
• Si5347: 4 input, 8 output, 64-QFN 9×9 mm
• Si5346: 4 input, 4 output, 44-QFN 7×7 mm
Applications
• OTN Muxponders and Transponders
• 10/40/100G network line cards
• GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)
• Carrier Ethernet switches
• Broadcast video
25-54 MHz XTAL
XA
OSC
IN0
4 Input
Clocks
IN1
IN2
IN3
÷FRAC
÷FRAC
÷FRAC
÷FRAC
DSPLL A
DSPLL B
DSPLL C
DSPLL D
XB
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
Status Flags
I2C / SPI
Status Monitor
Control
NVM
OUT0
Si5346A/B
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
Si5347A/B
Si5347C/D
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Si5347/46 Rev D Data Sheet
Feature List
1. Feature List
The Si5347/46-D features are listed below:
• Four or two DSPLLs to synchronize to multiple inputs
• Generates any combination of output frequencies from any in-
put frequency
• Ultra low jitter:
• 95 fs typ (12 kHz – 20 MHz)
• Input frequency range:
• Differential: 8 kHz to 750 MHz
• LVCMOS: 8 kHz to 250 MHz
• Output frequency range:
• Differential: up to 712.5 MHz
• LVCMOS: up to 250 MHz
• Flexible crosspoints route any input to any output clock
• Programmable jitter attenuation bandwidth per DSPLL: 0.1 Hz
to 4 kHz
• Highly configurable outputs compatible with LVDS, LVPECL,
LVCMOS, CML, and HCSL with programmable signal ampli-
tude
• Status monitoring (LOS, OOF, LOL)
• Hitless input clock switching: automatic or manual
•
•
•
•
•
•
Locks to gapped clock inputs
Automatic free-run and holdover modes
Fastlock feature for low nominal bandwidths
Glitchless on-the-fly DSPLL frequency changes
DCO mode: as low as 0.01 ppb steps per DSPLL
Core voltage:
• V
DD
: 1.8 V ±5%
• V
DDA
: 3.3 V ±5%
• Independent output clock supply pins: 3.3, 2.5, or 1.8 V
• Output-output skew:
• Using same DSPLL: 65 ps (Max)
• Serial interface: I
2
C or SPI
• In-circuit programmable with non-volatile OTP memory
• ClockBuilder
™
Pro software tool simplifies device configuration
• Si5347: Quad DSPLL, 4 input, 8 output, 64-QFN 9×9 mm
• Si5346: Dual DSPLL, 4 input, 4 output, 44-QFN 7×7 mm
• Temperature range: –40 to +85 °C
• Pb-free, RoHS-6 compliant
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Si5347/46 Rev D Data Sheet
Ordering Guide
2. Ordering Guide
Table 2.1. Si5347/46 Ordering Guide
Ordering Part Number
Si5347A-D-GM
1,2
Si5347B-D-GM
1,2
Si5347C-D-GM
1,2
Si5347D-D-GM
1,2
Si5346A-D-GM
1,2
Si5346B-D-GM
1,2
Si5347-D-EVB
Si5346-D-EVB
—
—
—
—
2
4
4
Number Of
DSPLLs
4
Number of
Outputs
8
Output Clock
Frequency Range
0.0001 to 712.5 MHz
0.0001 to 350 MHz
0.0001 to 712.5 MHz
0.0001 to 350 MHz
0.0001 to 712.5 MHz
0.0001 to 350 MHz
—
—
44-Lead 7x7
QFN
Evaluation
Board
—
—
—
—
Package
64-Lead 9x9
QFN
RoHS-6,
Pb-Free
Yes
Temp Range
–40 to 85 °C
Notes:
1. Add an R at the end of the device part number to denote tape and reel ordering options.
2. Custom, factory pre-programmed devices are available. Ordering part numbers are assigned by the ClockBuilder Pro software.
Part number format is: Si5347A-Dxxxxx-GM or Si5346A-Dxxxxx-GM, where “xxxxx” is a unique numerical sequence representing
the pre-programmed configuration.
Si534fg-Rxxxxx-GM
Timing product family
f = Multi-PLL clock
family
member (7, 6)
g = Device
grade
(A, B, C, D)
Product
Revision*
Custom ordering part number (OPN) sequence ID**
Package, ambient temperature range (QFN, -40 °C to +85°C)
*See Ordering Guide table for current product revision
** 5 digits; assigned by ClockBuilder Pro
Figure 2.1. Ordering Part Number Fields
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Si5347/46 Rev D Data Sheet
Functional Description
3. Functional Description
The Si5347 takes advantage of Silicon Labs’ 4
th
generation DSPLL technology to offer the industry’s most integrated and flexible jitter
attenuating clock generator solution. Each of the DSPLLs operate independently from each other and are controlled through a common
serial interface. Each DSPLL has access to any of the four inputs (IN0 to IN3) with manual or automatic input selection. Any of the
output clocks (OUT0 to OUT7) can be configured to any of the DSPLLs using a flexible crosspoint connection. The Si5346 is a smaller
form factor dual DSPLL version with four inputs and four outputs.
3.1 Frequency Configuration
The frequency configuration for each of the DSPLLs is programmable through the serial interface and can also be stored in non-volatile
memory. The combination of fractional input dividers (P
n
/P
d
), fractional frequency multiplication (M
n
/M
d
), and integer output division
(R
n
) allows each of the DSPLLs to lock to any input frequency and generate virtually any output frequency. All divider values for a spe-
cific frequency plan are easily determined using the ClockBuilder Pro utility.
3.2 DSPLL Loop Bandwidth
The DSPLL loop bandwidth determines the amount of input clock jitter attenuation. Register-configurable DSPLL loop bandwidth set-
tings in the range of 0.1 Hz to 4 kHz are available for selection for each of the DSPLLs. Since the loop bandwidth is controlled digitally,
each of the DSPLLs will always remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection.
3.2.1 Fastlock Feature
Selecting a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The fastlock feature allows setting
a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will ena-
ble the DSPLLs to lock faster. Fastlock Loop Bandwidth settings in the range of 100 Hz to 4 kHz are available for selection. Once lock
acquisition has completed, the DSPLL’s loop bandwidth will automatically revert to the DSPLL Loop Bandwidth setting, as described in
Section
3.2 DSPLL Loop Bandwidth.
The fastlock feature can be enabled or disabled independently for each of the DSPLLs.
3.3 Modes of Operation
Once initialization is complete, each of the DSPLLs operates independently in one of four modes: Free-run Mode, Lock Acquisition
Mode, Locked Mode, or Holdover Mode. A state diagram showing the modes of operation is shown in
Figure 3.1 Modes of Operation
on page 4.
The following sections describe each of these modes in greater detail.
3.3.1 Initialization and Reset
Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from
NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initializa-
tion period is complete. No clocks will be generated until the initialization is complete. There are two types of resets available. A hard
reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits will be re-
stored to their initial state including the serial interface. A hard reset is initiated using the RSTb pin or by asserting the hard register
reset bit. A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes. A hard reset affects all
DSPLLs, while a soft reset can either affect all or each DSPLL individually.
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Si5347/46 Rev D Data Sheet
Functional Description
Power-Up
Reset and
Initialization
No valid
input clocks
selected
Free-run
Valid input clock
selected
An input is
qualified and
available for
selection
Lock Acquisition
(Fast Lock)
Phase lock on
selected input
clock is achieved
No valid input
clocks available
for selection
Holdover
Mode
Locked
Mode
Input Clock
Switch
Selected input
clock fails
Yes
Other Valid
Clock Inputs
No Available?
Yes
No
Holdover
History
Valid?
Figure 3.1. Modes of Operation
3.3.2 Free-run Mode
Once power is applied to the Si5347 and initialization is complete, all four DSPLLs will automatically enter Free-run Mode. The frequen-
cy accuracy of the generated output clocks in Free-run Mode is entirely dependent on the frequency accuracy of the external crystal or
reference clock on the XA/XB pins. For example, if the crystal frequency is ±100 ppm, then all the output clocks will be generated at
their configured frequency ±100 ppm in Free-run Mode. Any drift of the crystal frequency will be tracked at the output clock frequencies.
A TCXO or OCXO is recommended for applications that need better frequency accuracy and stability while in Free-run Mode or Hold-
over Mode.
3.3.3 Lock Acquisition Mode
Each of the DSPLLs independently monitors its configured inputs for a valid clock. If at least one valid clock is available for synchroni-
zation, a DSPLL will automatically start the lock acquisition process.
If the fast lock feature is enabled, a DSPLL will acquire lock using the Fastlock Loop Bandwidth setting and then transition to the DSPLL
Loop Bandwidth setting when lock acquisition is complete. During lock acquisition the outputs will generate a clock that follows the VCO
frequency change as it pulls-in to the input clock frequency.
3.3.4 Locked Mode
Once locked, a DSPLL will generate output clocks that are both frequency and phase locked to their selected input clocks. At this point,
any XTAL frequency drift will not affect the output frequency. Each DSPLL has its own LOLb pin and status bit to indicate when lock is
achieved. See
3.7.4 LOL Detection
for more details on the operation of the loss of lock circuit.
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