LTC1426
Micropower
Dual 6-Bit PWM DAC
FEATURES
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DESCRIPTION
The LTC
®
1426 is a dual micropower 6-bit PWM DAC
featuring versatile PWM outputs and a flexible pushbutton
compatible digital interface. The DAC outputs provide a
PWM signal that swings from 0V to V
REF
, allowing the full-
scale output to be varied by adjusting the voltage at V
REF
.
The PWM output frequency is typically 5kHz, easing
output filtering requirements. V
CC
supply current is typi-
cally 50µA and drops to 0.2µA in shutdown.
The LTC1426 can be controlled using one of two interface
modes: pushbutton and pulse. The LTC1426 automati-
cally configures itself into the appropriate mode at start-
up by monitoring the state of the CLK pins. In pushbutton
mode, the CLK pins can be directly connected to external
pushbuttons to control the DAC output. In pulse mode,
the CLK pins can be connected to CMOS compatible
logic. The DAC outputs initially power up at half scale and
the contents of the internal DAC registers are retained in
shutdown.
The LTC1426 is available in 8-pin MSOP and SO packages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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Wide Supply Range: 2.7V
≤
V
CC
≤
5.5V
Wide Reference Voltage Range: 0V to 5.5V
Two Interface Modes:
Pulse Mode (Increment Only)
Pushbutton Mode (Increment/Decrement)
Low Supply Current: 50µA
0.2µA Supply Current in Shutdown
Available in 8-Pin MSOP and SO Packages
DAC Contents Are Retained in Shutdown
DACs Power-Up at Midrange
Low Output Impedance: < 100Ω
Output Frequency: 5kHz Typ
APPLICATIONS
s
s
s
s
s
LCD Contrast and Backlight Brightness Control
Power Supply Voltage Adjustment
Battery Charger Voltage and Current Adjustment
GaAs FET Bias Adjustment
Trimmer Pot Elimination
TYPICAL APPLICATION
Pushbutton Adjustable CCFL/LCD Contrast Generator
UP TO 6mA
LAMP
HIGH VOLTAGE
ROYER
16
15
14
13
12
11
10
9
5V
C9
2.2µF
8V TO
28V
5V
R1
44.2k
1%
C1
0.1µF
R2
44.2k
1%
C2
1µF
C7 1µF
I
CCFL
= 0µA TO 50µA
1
2
3
4
5
6
7
CCFL PGND CCFL V
SW
I
CCFL
DIO
CCFL V
C
AGND
SHDN
LCD V
C
LT1182
BULB
BAT
ROYER
V
IN
FBP
FBN
LCD V
SW
R
P1
47k
UP
R
P2
47k
UP CONTRAST
UP/DOWN 1
CCFL UP/DOWN 2
3
R
SHDN
1M
SHDN
LTC1426
CLK1
CLK2
GND
SHDN
V
CC
V
REF
8
7
6
5
R5
20k
1%
DOWN
DOWN
4
PWM1 PWM2
R3
5.1k
1%
R4
4.99k
1%
C3
10µF
R7 8
C8 10k
LCD PGND
0.68µF
C4
0.1µF
R6
40k
1%
CONSULT THE LT1182 DATA SHEET FOR
DETAILS ON THE HIGH VOLTAGE ROYER
AND LCD CONTRAST CONVERTER SECTIONS
U
U
U
+
C10
2.2µF
35V
+
C11
2.2µF
35V
LCD
CONTRAST
CONVERTER
V
OUT
NEGATIVE
LCD CONTRAST
V
OUT
= –10V TO –30V
1426 TA01
1
LTC1426
ABSOLUTE
MAXIMUM
RATINGS
(Note 1)
PACKAGE/ORDER INFORMATION
TOP VIEW
CLK1 1
CLK2 2
GND 3
PWM1 4
8 SHDN
7 V
CC
6 V
REF
5 PWM2
Total Supply Voltage (V
CC
) ........................................ 7V
Reference Voltage (V
REF
) ............................... – 0.3 to 7V
Input Voltage (All Inputs) .............. – 0.3 to (V
CC
+ 0.3V)
DAC Output Short-Circuit Duration.................. Indefinite
I
PWM(MAX)
.......................................................... 100mA
Operating Temperature Range
LTC1426C................................................ 0°C to 70°C
LTC1426I........................................... – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
LTC1426CMS8
LTC1426CS8
LTC1426IS8
MS8 PART MARKING
LTBQ
S8 PART MARKING
1426
1426I
MS8 PACKAGE
S8 PACKAGE
8-LEAD PLASTIC MSOP 8-LEAD PLASTIC SO
T
JMAX
= 100°C,
θ
JA
= 200°C/ W (MS8)
T
JMAX
= 100°C,
θ
JA
= 130°C/ W (S8)
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER
V
CC
V
REF
I
CC
Supply Voltage
Reference Voltage
Supply Current
CONDITIONS
T
A
= 25°C, (Note 2) unless otherwise specified.
MIN
q
q
TYP
MAX
5.5
5.5
UNITS
V
V
µA
µA
µA
µA
µA
µA
bits
kHz
kHz
Ω
%
%
2.7
0
40
50
0.2
75
75
0.2
6
3
2
5
5
20
98.44
0
Pulse Mode: V
SHDN
= V
CC
, V
CLK1
= V
CLK2
= 0V, PWM1 = PWM2 = NC
Pushbutton Mode: V
SHDN
= V
CC
, V
CLK1
= V
CLK2
= PWM1 = PWM2 = NC
SHDN = 0 (Note 3)
Pulse Mode: V
SHDN
= V
CC
, V
CLK1
= V
CLK2
= 0V, PWM1 = PWM2 = NC
Pushbutton Mode: V
SHDN
= V
CC
, V
CLK1
= V
CLK2
= PWM1 = PWM2 = NC
SHDN = 0 (Note 3)
0°C
≤
T
A
≤
70°C
– 40°C
≤
T
A
≤
85°C
V
CC
= 2.7V, V
REF
= 0.5V
q
q
q
q
q
q
100
100
±10
150
150
±10
6
6
100
I
REF
Reference Current
DAC Resolution
DAC Frequency
DAC Output Impedance
DAC Full-Scale Duty Cycle
DAC Zero-Scale Duty Cycle
DNL
INL
FS Error
I
IN
DAC Differential Nonlinearity
DAC Integral Nonlinearity
DAC Full-Scale Error
Logic Input Current
Pulse Mode: 0V
≤
V
IN
≤
V
CC
Pushbutton Mode: 0V
≤
V
IN
≤
V
CC
V
IH
CLK High Level
Input Voltage (Note 5)
V
CC
= 5.5V
V
CC
= 3.6V
SHDN
CLK1, CLK2
SHDN
CLK1, CLK2
SHDN
CLK1, CLK2
SHDN
CLK1, CLK2
Monotonicity Guaranteed (Note 4)
(Note 4)
q
q
q
q
q
q
q
q
q
q
q
q
q
q
±0.05
±0.05
±0.50
±5
±5
±5
±10
2.0
4.4
1.9
2.9
2
U
W
U
U
W W
W
LSB
LSB
LSB
µA
µA
µA
µA
V
V
V
V
LTC1426
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER
V
IL
CLK Low Level
Input Voltage (Note 5)
CONDITIONS
V
CC
= 4.5V
V
CC
= 2.7V
I
OZ
Z
IN
f
CLK
t
CKHI
t
CKLO
t
PW
t
DEB
t
DELAY
f
REPEAT
Three-State Output Leakage
CLK Input Resistance
Clock Frequency
Clock High Time
Clock Low Time
Pulse Width
Debounce Time
Repeat Rate Delay
Repeat Frequency
SHDN = 0
T
A
= 25°C, (Note 2) unless otherwise specified.
MIN
SHDN
CLK1, CLK2
SHDN
CLK1, CLK2
q
q
q
q
q
TYP
MAX
0.8
0.8
0.45
0.45
±5
UNITS
V
V
V
V
µA
MΩ
MHz
kHz
ns
ns
ns
ns
µs
Pushbutton Mode, CLK1/CLK2
Pulse Mode, V
CC
= 3.3V
Pulse Mode, V
CC
= 2.7V
Pulse Mode, V
CC
= 3.3V
Pulse Mode, V
CC
= 2.7V
Pulse Mode, V
CC
= 3.3V
Pulse Mode, V
CC
= 2.7V
Pushbutton Mode
Pushbutton Mode
Pushbutton Mode
Pushbutton Mode
q
q
q
q
q
q
q
q
q
q
2.5
1
750
450
600
450
600
670
10.7
340
11.7
12.8
410
19.5
21.3
680
23.4
ms
ms
Hz
The
q
denotes the specifications which apply over the full operating
temperature range.
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2:
All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground, unless otherwise
specified. All typicals are given for V
CC
= V
REF
= 5V, T
A
= 25°C and
PWM1/PWM2 output to GND, C
PWM
= 10pF.
Note 3:
Shutdown current can be negative due to leakage currents if V
CC
>
V
REF
or V
REF
> V
CC
.
Note 4:
Guaranteed by Design. Decouple the V
CC
and V
REF
pins to GND
using high quality, low ESR, low ESL 0.1µF capacitors to eliminate PWM
switching noise that may otherwise get coupled into the CLK1/CLK2 high
impedance input buffers. The decoupling capacitors should be located in
close proximity to these pins and the ground line to have maximum effect.
Note 5:
Input thresholds apply for both pushbutton and pulse modes.
TYPICAL PERFORMANCE CHARACTERISTICS
Differential Nonlinearity (DNL)
0.05
V
CC
= V
REF
= 5V
0.04 T
A
= 25°C
0.03
DNL ERROR (LSB)
0.05
0.04
0.03
0.02
OUTPUT PULL-DOWN VOLTAGE (mV)
0.02
0.01
0
– 0.01
– 0.02
– 0.03
– 0.04
– 0.05
0
8
16
24
32 40
CODE
48
56
64
ERROR (LSB)
U W
1426 G01
Integral Nonlinearity (INL)
V
CC
= V
REF
= 5V
T
A
= 25°C
Output Pull-Down Voltage
vs Output Current Sink Capability
1000
V
CC
= 5V
85°C
25°C
– 40°C
10
100
0.01
0
– 0.01
– 0.02
– 0.03
– 0.04
– 0.05
0
8
16
24
32 40
CODE
48
56
64
1
0.1
0.1
1
10
100
OUTPUT CURRENT SINK CAPABILITY (mA)
1426 G03
1426 G02
3
LTC1426
TYPICAL PERFORMANCE CHARACTERISTICS
Minimum Clock High Time
vs Temperature
600
500
400
V
CC
= 3V
300
200
V
CC
= 5V
100
0
– 40
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
CLOCK HIGH TIME (ns)
– 15
10
35
TEMPERATURE (°C)
PIN FUNCTIONS
CLK1 (Pin 1):
Channel 1 Clock/Pushbutton Input.
CLK2 (Pin 2):
Channel 2 Clock/Pushbutton Input.
GND (Pin 3):
Ground. It is recommended that GND be tied
to a ground plane.
PWM1 (Pin 4):
Channel 1 PWM Output.
PWM2 (Pin 5):
Channel 2 PWM Output.
V
REF
(Pin 6):
Voltage Reference Input. V
REF
powers the
DAC output buffers and can be used to control the output
span. Bypass V
REF
to GND with an external capacitor to
minimize output errors. V
REF
can be tied to V
CC
if desired.
V
CC
(Pin 7):
Voltage Supply. This supply must be kept free
from noise and ripple by bypassing directly to the ground
plane.
SHDN (Pin 8):
Shutdown. A logic low puts the chip into
shutdown mode with the PWM outputs in high imped-
ance. The digital settings for the DACs are retained in
shutdown.
TI I G DIAGRA S
Pulse Mode Timing
t
CKL0
CLK1
CLK2
1426 TC01
4
U W
60
1426 G04
Supply Current
vs Logic Input Voltage
38.5
36.5
34.5
32.5
30.5
28.5
26.5
24.5
22.5
85
60
Supply Current vs Temperature
V
CC
= 5V
50
40
30
20
10
0
– 40
PULSE
MODE
PUSHBUTTON
MODE
PUSHBUTTON
MODE
PULSE
MODE
T
A
= 25°C
CLK1 AND CLK2
TIED TOGETHER
0
1
3
4
2
LOGIC INPUT VOLTAGE (V)
5
1426 F05
– 15
10
35
TEMPERATURE (°C)
60
85
1426 G06
W
U
U
UW
U
Pushbutton Mode Timing
t
PW
CLK1
CLK2
t
CKHI
1426 TC02
LTC1426
BLOCK DIAGRAM
W
POWER-ON
RESET
LATCH
AND
LOGIC
MODE SELECT
0 = PUSHBUTTON MODE
1 = PULSE MODE
V
REF
6
COMPARATOR
DRIVER
PWM1
6-BIT
UP/DOWN
COUNTER
CONTROL
LOGIC
6-BIT
UP/DOWN
COUNTER
6-BIT
UP
COUNTER
6
COMPARATOR
6
DRIVER
PWM2
SHDN
OSCILLATOR
1426 F01
CLK1
CLK2
INPUT
CONDITIONING
DEBOUNCE
CIRCUIT
Figure 1. LTC1426 Block Diagram
DEFI ITIO S
LSB:
The least significant bit or the ideal duty cycle
difference between two successive codes.
LSB = DC
MAX
/64
DC
MAX
= The DAC output maximum duty cycle
Resolution:
The resolution is the number of DAC output
states (64) that divide the full-scale output duty cycle
range. The resolution does not necessarily imply linearity.
INL:
End point integral nonlinearity is the maximum devia-
tion from a straight line passing through the end points of
the DAC transfer curve. The INL error at a given code is
calculated as follows:
INL = (DC
OUT
– DC
IDEAL
)/LSB
DC
IDEAL
= (Code)(LSB)
DC
OUT
= the DAC output duty cycle measured at the
given number of clocked in pulses.
DNL:
Differential nonlinearity is the difference between the
measured duty cycle change and the ideal 1LSB duty cycle
change between any two adjacent codes. The DNL error
between any two codes is calculated as follows:
DNL = (∆DC
OUT
– LSB)/LSB
∆DC
OUT
= The measured duty cycle difference between
two adjacent codes.
Full-Scale Error:
Full-scale error is the difference between
the ideal and measured DAC output duty cycles with all bits
set to one (Code = 63). The full-scale error is calculated as
follows:
FSE = (DC
OUT
– DC
IDEAL
)/LSB
DC
IDEAL
= DC
MAX
APPLICATIONS INFORMATION
Dual 6-Bit PWM DAC
Figure 1 shows a block diagram of the LTC1426. Each
6-bit PWM DAC is guaranteed monotonic and is digitally
adjustable in 64 equal steps, which corresponds from 0%
to 98.5% duty cycle full scale. At power-up, the counters
reset to 100000B and both DAC outputs assume midscale
duty cycle. The PWM outputs have an output impedance
of less than 100Ω. The DAC outputs swing from 0V to the
reference voltage, V
REF
, which can be biased from 0V to
5.5V. The frequency of the DAC outputs is above 3kHz,
easing output filtering.
In the case of a pure resistive load, the voltage measured
across load RL is given by:
V = (V
PWM
)R
L
/(R
L
+ R
OUT
)
U
W
U
U
U
U
5
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