CED71A3/CEU71A3
Dec. 2002
N-Channel Logic Level Enhancement Mode Field Effect Transistor
FEATURES
30V , 65A , R
DS(ON)
=10m
Ω
@V
GS
=10V.
R
DS(ON)
=14m
Ω
@V
GS
=5.0V.
Super high dense cell design for extremely low R
DS(ON)
.
High power and current handling capability.
TO-252 & TO-251 package.
D
6
G
D
G
S
G
D
S
CEU SERIES
TO-252AA(D-PAK)
CED SERIES
TO-251(l-PAK)
S
ABSOLUTE MAXIMUM RATINGS (Tc=25 C unless otherwise noted)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current-Continuous
-Pulsed
Drain-Source Diode Forward Current
Maximum Power Dissipation
@Tc=25 C
Derate above 25 C
Operating and Storage Temperature Range
Symbol
V
DS
V
GS
I
D
I
DM
I
S
P
D
T
J
, T
STG
Limit
30
20
65
100
65
69
0.56
-55 to 150
Unit
V
V
A
A
A
W
W/ C
C
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
R
JC
R
JA
6-67
1.8
40
C/W
C/W
CED71A3/CEU71A3
ELECTRICAL CHARACTERISTICS (T
C
=25 C unless otherwise noted)
Parameter
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
BV
DSS
I
DSS
I
GSS
V
GS(th)
R
DS(ON)
I
D(ON)
g
FS
C
ISS
C
OSS
C
RSS
b
Symbol
Condition
V
GS
= 0V, I
D
= 250µA
V
DS
= 30V, V
GS
= 0V
V
GS
= 20V, V
DS
= 0V
V
DS
= V
GS
, I
D
= 250µA
V
GS
= 10V, I
D
= 15A
V
GS
= 5.0V, I
D
= 13A
V
GS
= 10V, V
DS
= 5V
V
DS
= 5V, I
D
= 12A
Min Typ Max Unit
30
1
V
µA
100 nA
1
8.5
65
26
2152
965
234
3
10
11.5 14
V
mΩ
mΩ
A
S
P
F
P
F
P
F
6
Zero Gate Voltage Drain Current
Gate-Body Leakage
ON CHARACTERISTICS
a
Gate Threshold Voltage
Drain-Source On-State Resistance
On-State Drain Current
Forward Transconductance
DYNAMIC CHARACTERISTICS
b
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V
DS
=15V, V
GS
= 0V
f =1.0MH
Z
SWITCHING CHARACTERISTICS
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
t
D(ON)
t
r
t
D(OFF)
t
f
Q
g
Q
gs
Q
gd
V
DD
= 15V,
I
D
=1A,
V
GS
= 10V,
R
GEN
=6
Ω
30
63
73
59
55
60
110
130
100
67
ns
ns
ns
ns
nC
nC
nC
V
DS
=10V, I
D
= 15A,
V
GS
=10V
6-68
9
18
CED71A3/CEU71A3
ELECTRICAL CHARACTERISTICS (T
C
=25 C unless otherwise noted)
Parameter
Diode Forward Voltage
Symbol
V
SD
Condition
V
GS
= 0V, Is = 2.3A
Min Typ Max Unit
0.9
1.3
V
DRAIN-SOURCE DIODE CHARACTERISTICS
a
Notes
a.Pulse Test:Pulse Width 300 s, Duty Cycle 2%.
b.Guaranteed by design, not subject to production testing.
60
V
GS
=10,8,6,4V
50
50
60
6
I
D
, Drain Current (A)
I
D
, Drain Current (A)
40
30
20
10
0
0
1
2
3
4
5
40
30
-55 C
20
25 C
10
0
1
2
3
4
Tj=125 C
V
GS
=3V
V
DS
, Drain-to-Source Voltage (V)
V
GS
, Gate-to-Source Voltage (V)
Figure 1. Output Characteristics
3000
Figure 2. Transfer Characteristics
1.80
R
DS(ON)
, Normalized
R
DS(ON)
,
On-Resistance(Ohms)
2500
1.60
1.40
1.20
1.00
0.80
I
D
=15A
V
GS
=10V
C, Capacitance (pF)
Ciss
2000
1500
1000
500
0
0
5
10
15
20
25
30
Coss
Crss
0.60
-50 -25
0
25
50
75
100 125 150
V
DS
, Drain-to Source Voltage (V)
T
J
, Junction Temperature( C)
Figure 3. Capacitance
Figure 4. On-Resistance Variation with
Temperature
6-69
CED71A3/CEU71A3
BV
DSS
, Normalized
Drain-Source Breakdown Voltage
Vth, Normalized
Gate-Source Threshold Voltage
1.30
1.20
1.10
1.00
0.90
0.80
0.70
0.60
-50 -25
0
25 50
75 100 125 150
V
DS
=V
GS
I
D
=250 A
1.15
I
D
=250 A
1.10
1.05
1.00
0.95
0.90
0.85
-50 -25
6
0
25
50
75 100 125 150
Tj, Junction Temperature ( C)
Tj, Junction Temperature ( C)
Figure 5. Gate Threshold Variation
with Temperature
50
Figure 6. Breakdown Voltage Variation
with Temperature
50
g
FS
, Transconductance (S)
Is, Source-drain current (A)
40
30
20
10
V
DS
=5V
0
0
10
20
30
40
10
1.0
0.1
0.4
0.6
0.8
1.0
1.2
1.4
I
DS
, Drain-Source Current (A)
V
SD
, Body Diode Forward Voltage (V)
Figure 7. Transconductance Variation
with Drain Current
10
8
6
4
2
0
0
15
30
45
60
Figure 8. Body Diode Forward Voltage
Variation with Source Current
2
V
GS
, Gate to Source Voltage (V)
V
DS
=15V
I
D
=15A
10
1m
S(
)
ON
Li
t
mi
s
10
m
I
D
, Drain Current (A)
10
1
10
0
-1
s
10
RD
0m
s
1s
D
C
10
10
-2
T
A
=25 C
R
JA
=
40 C/W
Single Pulse
10
-1
10
0
10
1
10
-2
10
2
Qg, Total Gate Charge (nC)
V
DS
, Drain-Source Voltage (V)
Figure 9. Gate Charge
6-70
Figure 10. Maximum Safe
Operating Area
CED71A3/CEU71A3
4
V
IN
D
V
GS
R
GEN
G
90%
V
DD
t
on
R
L
V
OUT
V
OUT
10%
t
off
t
r
90%
t
d(on)
t
d(off)
90%
10%
t
f
INVERTED
6
S
V
IN
50%
10%
50%
PULSE WIDTH
Figure 11. Switching Test Circuit
Figure 12. Switching Waveforms
10
0
r(t),Normalized Effective
Transient Thermal Impedance
D=0.5
0.2
10
-1
0.1
0.05
0.02
P
DM
t
1
0.01
t
2
1. R
JA
(t)=r (t) * R
JA
2. R
JA
=See Datasheet
3. T
JM-
T
A
= P* R
JA
(t)
4. Duty Cycle, D=t1/t2
10
-2
10
-2
Single Pulse
-3
10
10
-4
10
-3
10
-1
10
0
10
1
10
2
Square Wave Pulse Duration (sec)
Figure 13. Normalized Thermal Transient Impedance Curve
6-71
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