IDT709149S
HIGH-SPEED 36K (4K x 9-BIT)
OBSOLETE PART
SYNCHRONOUS PIPELINED
DUAL-PORT SRAM
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
Features
◆
◆
◆
◆
◆
Architecture based on Dual-Port SRAM cells
– Allows full simultaneous access from both ports
High-speed clock-to-data output times
– Commercial: 8/10/12ns (max.)
– Industrial: 10ns (max.)
Low-power operation
– IDT709149S
Active: 1500mW (typ.)
Standby: 75mW (typ.)
4K X 9 bits
13ns cycle time, 76MHz operation in pipeline mode
– Self-timed write allows for fast cycle times
◆
Functional Block Diagram
I/O
0-8L
OE
L
CLK
L
T OR
R F
A D
P E
E D
T N
S
E E
L M IGN
O M S
S
B O DE
O EC
R EW
T N
O
N
◆
◆
◆
◆
◆
Synchronous operation
– 4ns setup to clock, 1ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 8ns clock to data out
TTL-compatible, single 5V (±10%) power supply
Clock Enable feature
Guaranteed data output hold times
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
REGISTER
REGISTER
WRITE
LOGIC
MEMOR
MEMORY
Y
ARRAY
ARRAY
WRITE
LOGIC
I/O
0-8R
FT/PIPED
R
0/1
SENSE
AMPS
DECODER DECODER
SENSE
AMPS
0
1
REG
en
REG
en
CLKEN
L
Self-
timed
Write
Logic
Self-
timed
Write
Logic
OE
R
CLK
R
CLKEN
R
R/W
L
CE
L
REG
REG
R/W
R
CE
R
3494 drw 01
A
0L
-A
11L
A
0R
-A
11R
FEBRUARY 2018
1
©2018 Integrated Device Technology, Inc.
DSC-34948
IDT709149S
High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT709149 is a high-speed 4K x 9 bit synchronous Dual-Port
SRAM. The memory array is based on Dual-Port memory cells to allow
simultaneous access from both ports. Registers on control, data, and
address inputs provide low set-up and hold times. The timing latitude
provided by this approach will allow systems to be designed with very short
cycle times. This device has been optimized for applications having
unidirectional data flow or bi-directional data flow in bursts, by utilizing input
data registers.
The IDT709149 utilizes a 9-bit wide data path to allow for parity at the
user's option. This feature is especially useful in data communication
applications where it is necessary to use a parity bit for transmission/
reception error checking.
Fabricated using CMOS high-performance technology, these Dual-
Ports typically operate on only 800mW of power at maximum high-speed
clock-to-data output times as fast as 8ns. An automatic power down
feature, controlled by
CE,
permits the on-chip circuitry of each port to enter
a very low standby power mode.
The IDT709149 is packaged in an 80-pin TQFP.
Pin Configurations
(1,2,3)
N/C
N/C
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
CLKEN
L
CLK
L
CLK
R
CLKEN
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
N/C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
Reference
N/C
A
6L
A
7L
A
8L
A
9L
A
10L
A
11L
N/C
OE
L
V
CC
V
CC
R/W
L
N/
N/C
C
CE
L
GND
I/O
8L
I/O
7L
I/O
6L
N/C
IDT709149PF
PN80
(4)
80-Pin TQFP
Top View
(5)
N/C
A
7R
A
8R
A
9R
A
10R
A
11R
N/C
OE
R
FT/PIPED
R
GND
GND
R/W
R
N/C
N/C
CE
R
GND
I/O
8R
I/O
7R
I/O
6R
N/C
3494 drw 02
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All ground pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4, This package code is used to reference the package diagram.
5. This text does not indicate the orientaion of the actual part-marking.
N/C
N/C
I/O
5L
V
CC
I/O
4L
I/O
3L
I/O
2L
I/O
1L
I/O
0L
GND
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
V
CC
I/O
4R
I/O
5R
N/C
N/C
6.42
2
IDT709149S
High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Terminal Voltage
Temperature
Under Bias
Storage
Temperature
DC Output Current
Commercial
& Industrial
-0.5 to +7.0
Unit
V
Maximum Operating Temperature
and Supply Voltage
(1)
Grade
Commercial
Ambient Temperature
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
Vcc
5.0V
+
10%
5.0V
+
10%
3494 tbl 02
V
TERM
(2)
T
BIAS
T
STG
I
OUT
-0.5 to V
CC
-55 to +125
-65 to +150
50
V
o
Industrial
C
C
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
o
mA
3494 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
cc
+ 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> V
cc
+ 10%.
Recommended DC Operating
Conditions
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
____
Max.
5.5
0
6.0
(2)
0.8
Unit
V
V
V
V
3494 tbl 03
Capacitance
(T
A
= +25°C, f = 1.0MH
z
)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
8
9
Unit
pF
pF
3494 tbl 04
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed V
cc
+ 10%.
NOTES:
1. These parameters are determined by device characterization, but are not produc-
tion tested.
2. 3dV references the interpolated capacitance when the input and output switch from
0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
CC
= 5.0V ± 10%)
709149S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 5.5V, V
IN
= 0V to V
CC
V
OUT
= 0V to V
CC
I
OL
= +4mA
I
OH
= -4mA
Min.
___
___
___
Max.
10
10
0.4
___
Unit
µA
µA
V
V
3494 tbl 05
2.4
NOTE:
1. At V
CC
< 2.0V, input leakages are undefined
3
6.42
IDT709149S
High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(4)
(V
CC
= 5V ± 10%)
709149S8
Com'l Only
Symbol
I
CC
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Ports - All
CMOS Level Inputs)
Full Standby Current
(One Port - All
CMOS Level Inputs)
Test Condition
CE
L
and
CE
R
= V
IL
,
Outputs Disabled
f = f
MAX
(1)
CE
L
and
CE
R
= V
IH
f = f
MAX
(1)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(3)
Active Port Outputs Disabled,
f=f
MAX
(1)
CE
L
and
CE
R
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(2)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(3)
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled,
f = f
MAX
(1)
Version
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
Typ.
200
____
709149S10
Com'l
& Ind
Typ.
190
190
90
90
170
170
5
5
160
160
Max.
310
340
150
175
220
250
15
20
210
240
709149S12
Com'l Only
Typ.
180
____
Max.
320
____
Max.
300
____
Unit
mA
I
SB1
100
____
150
____
85
____
140
____
mA
I
SB2
180
____
230
____
160
____
210
____
mA
I
SB3
5
____
15
____
5
____
15
____
mA
I
SB4
170
____
220
____
150
____
200
____
mA
NOTES:
1. At f = f
MAX
, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/t
CLK
, using "AC TEST CONDITIONS" at input levels of
GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc = 5V, T
A
= 25°C for Typ, and are not production tested. I
CC DC
= 150mA (Typ).
3494 tbl 06
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns Max.
1.5V
1.5V
Figures 1,2 and 3
3494 tbl 07
8
7
6
9pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
5V
5V
893Ω
893Ω
DATA
OUT
ΔtCD
(Typical, ns)
5
4
3
2
DATA
OUT
347Ω
30pF
347Ω
5pF*
1
0
,
3494 drw 03
3494 drw 04
,
-1
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
3494 drw 05
Figure 1. AC Output Test load.
Figure 2. Output Test Load
(For t
CKLZ
, t
CKHZ
, t
OLZ
, and t
OHZ
).
*Including scope and jig.
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.42
4
IDT709149S
High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range—
(Read and Write Cycle Timing)
709149S8
Com'l Only
Symbol
t
CYC1
t
CYC2
t
CH1
t
CL1
t
CH2
t
CL2
t
CD1
t
CD2
t
S
t
H
t
DC
t
CKLZ
t
CKHZ
t
OE
t
OLZ
t
OHZ
t
SCK
t
HCK
t
CWDD
Parameter
Clock Cycle Time (Flow-Through)
(3)
Clock Cycle Time (Pipelined)
(3)
Clock High Time (Flow-Through)
(3)
Clock Low Time (Flow-Through)
(3)
Clock High Time (Pipelined)
(3)
Clock Low Time (Pipelined)
(3)
Clock to Data Valid (Flow-Through)
(3)
Clock to Data Valid (Pipelined)
(3)
Registered Signal Set-up Time
Registered Signal Hold Time
Data Output Hold After Clock High
Clock High to Output Low-Z
(1,2)
Clock High to Output High-Z
(1,2)
Output Enable to Output Valid
Output Enable to Output Low-Z
(1,2)
Output Disable to Output High-Z
(1,2)
Clock Enable, Disable Set-Up Time
Clock Enable, Disable Hold Time
Write Port Clock High to Read Data Delay
Min.
16
13
6
6
6
6
____
____
709149S10
Com'l
& Ind
Min.
20
15
7
7
6
6
____
____
709149S12
Com'l Only
Min.
20
16
8
8
6
6
____
____
Max.
____
____
____
____
____
____
Max.
____
____
____
____
____
____
Max.
____
____
____
____
____
____
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3494 tbl 08
12
8
____
____
____
____
15
10
____
____
____
____
20
12
____
____
____
____
4
1
1
2
____
____
4
1
1
2
____
____
5
1
1
2
____
____
7
8
____
7
8
____
9
10
____
0
____
0
____
0
____
7
____
____
7
____
____
9
____
____
4
1
____
4
1
____
5
1
____
25
30
35
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The Pipelined output parameters (t
CYC2
, t
CD2
) always apply to the Left Port. The Right Port uses the Pipelined t
CYC2
and t
CD2
when
FT/PIPED
R
= V
IH
and the Flow-
Through parameters (t
CYC1
, t
CD1
) when
FT/PIPED
R
= V
IL.
5
6.42
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