NSPU3061
6.3 V Unidirectional ESD
and Surge Protection
Device
The NSPU3061 is designed to protect voltage sensitive components
from ESD. Excellent clamping capability, low leakage, high peak
pulse current handling capability and fast response time provide best
in class protection on designs that are exposed to ESD. Because of its
small size, it is suited for use in cellular phones, tablets, MP3 players,
digital cameras and many other portable applications where board
space comes at a premium.
Features
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MARKING
DIAGRAM
X2DFN2
CASE 714AB
6
M
6M
•
•
•
•
Low Clamping Voltage
Low Leakage
Small Body Outline: 1.0 mm x 0.6 mm
Protection for the Following IEC Standards:
IEC61000−4−2 Level 4:
±30
kV Contact Discharge
IEC61000−4−5 (Lightning): 30 A (8/20
ms)
•
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
= Specific Device Code
= Date Code
1
CATHODE
2
ANODE
•
USB V
BUS
and CC Line Protection
•
Microphone Line Protection
•
GPIO Protection
Table 1. MAXIMUM RATINGS
Rating
IEC 61000−4−2 (ESD)
Contact
Air
Operating Junction Temperature Range
Storage Temperature Range
Minimum Peak Pulse Current
T
J
T
STG
I
PP
Symbol
Value
±30
±30
−65 to +
150
−65 to +
150
30
°C
°C
A
Unit
kV
ORDERING INFORMATION
Device
NSPU3061N2T5G
Package
X2DFN2
(Pb−Free)
Shipping
†
8000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
©
Semiconductor Components Industries, LLC, 2016
1
September, 2018 − Rev. 2
Publication Order Number:
NSPU3061/D
NSPU3061
Table 2. ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Symbol
I
PP
V
C
V
RWM
I
R
V
BR
I
T
Parameter
Maximum Reverse Peak Pulse Current
Clamping Voltage @ I
PP
Working Peak Reverse Voltage
Maximum Reverse Leakage Current @ V
RWM
Breakdown Voltage @ I
T
Test Current
I
PP
V
C
V
BR
V
RWM
I
R
V
F
I
T
V
I
F
I
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
Uni−Directional Surge Protection
Table 3. ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise specified)
Parameter
Reverse Working Voltage
Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (Note 1)
Clamping Voltage TLP
(Note 2)
Symbol
V
RWM
V
BR
I
R
V
C
V
C
I/O Pin to GND
I
T
= 1 mA, I/O Pin to GND
V
RWM
= 6.3 V, I/O Pin to GND
IEC61000−4−2,
±
8 kV Contact
I
PP
= 8 A
IEC61000−4−2 Level 2 Equivalent
(±4 kV Contact,
±
8 kV Air)
6.4
6.9
0.02
See Figures 2 & 3
6.4
6.6
30
6.6
7.3
0.025
90
110
9.4
10.4
A
V
W
pF
Conditions
Min
Typ
Max
6.3
9.5
1
Unit
V
V
mA
V
V
I
PP
= 16 A IEC61000−4−2 Level 4 Equivalent
(±8 kV Contact,
±
15 kV Air)
Reverse Peak Pulse Current
Clamping Voltage 8x20
ms
Waveform per Figure 1
Dynamic Resistance
Junction Capacitance
I
PP
V
C
R
DYN
C
J
IEC61000−4−5 (8x20
ms)
per Figure 1
I
PP
= 20 A
I
PP
= 30 A
100 ns TLP
V
R
= 0 V, f = 1 MHz
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. For test procedure see application note AND8307/D
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z
0
= 50
W,
t
p
= 100 ns, t
r
= 4 ns, averaging window; t
1
= 30 ns to t
2
= 60 ns.
TYPICAL CHARACTERISTICS
100
% OF PEAK PULSE CURRENT
90
80
70
60
50
40
30
20
10
0
0
20
40
t, TIME (ms)
60
80
t
P
t
r
PEAK VALUE I
RSM
@ 8
ms
PULSE WIDTH (t
P
) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8
ms
HALF VALUE I
RSM
/2 @ 20
ms
Figure 1. 8 x 20
ms
Pulse Waveform
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NSPU3061
TYPICAL CHARACTERISTICS
40
35
30
VOLTAGE (V)
VOLTAGE (V)
0
20
40
60
TIME (ns)
80
100
120
140
25
20
15
10
5
0
−5
−20
10
5
0
−5
−10
−15
−20
−25
−30
−35
−20
0
20
40
60
TIME (ns)
80
100
120
140
Figure 2. ESD Clamping Voltage
Positive 8 kV Contact per IEC61000−4−2
20
18
16
14
I
TLP
(A)
12
10
8
6
4
2
0
0
1
2
3
4
5
6
7
8
9
V
CTLP
(V)
10
9
8
7
6
5
4
3
2
1
0
10
−20
−18
−16
−14
V
IEC
Eq (kV)
I
TLP
(A)
−12
−10
−8
−6
−4
−2
0
0
−1
Figure 3. ESD Clamping Voltage
Negative 8 kV Contact per IEC61000−4−2
10
9
8
7
6
5
4
3
2
1
0
−2
−3
−4
V
CTLP
(V)
−5
−6
−7
−8
V
IEC
Eq (kV)
Figure 4. Positive TLP I−V Curve
Figure 5. Negative TLP I−V Curve
9
8
7
V
C
@ I
PK
(V)
V
C
@ I
PK
(V)
0
5
10
15
20
25
30
35
40
45
6
5
4
3
2
1
0
I
PK
(A)
8
7
6
5
4
3
2
1
0
0
5
10
15
20
25
I
PK
(A)
30
35
40
45
50
Figure 6. Positive Clamping Voltage vs. Peak
Pulse Current (t
p
= 8/20
ms)
Figure 7. Negative Clamping Voltage vs. Peak
Pulse Current (t
p
= 8/20
ms)
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NSPU3061
TYPICAL CHARACTERISTICS
1E−03
1E−04
1E−05
1E−06
I
R
(A)
I
R
(A)
5
6
1E−07
1E−08
1E−09
1E−10
1E−11
0
1
2
3
4
V
R
(V)
7
8
1E−03
1E−04
1E−05
1E−06
1E−07
1E−08
1E−09
1E−10
1E−11
0
1
2
3
4
5
6
7
8
9
V
R
(V)
Figure 8. Breakdown Voltage
100
90
80
70
C (pF)
60
50
40
30
20
10
0
0
1
2
3
V
BIAS
(V)
4
Figure 9. Reverse Leakage Current
5
6
Figure 10. Line Capacitance,
f
= 1 MHz
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NSPU3061
Transmission Line Pulse (TLP) Measurement
ESD Voltage Clamping
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 11. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 12 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels. For more information
on TLP measurements and how to interpret them please
refer to AND9007/D.
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
IEC 61000−4−2 Spec.
Test Volt-
age (kV)
2
4
6
8
First Peak
Current
(A)
7.5
15
22.5
30
Current at
30 ns (A)
4
8
12
16
Current at
60 ns (A)
2
4
6
8
L
50
W
Coax
Cable
S
Attenuator
÷
10 MW
I
M
50
W
Coax
Cable
V
M
Level
1
DUT
V
C
Oscilloscope
2
3
4
Figure 11. Simplified Schematic of a Typical TLP
System
I
peak
100%
90%
IEC61000−4−2 Waveform
I @ 30 ns
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
Figure 13. IEC61000−4−2 Spec
Figure 12. Comparison Between 8 kV IEC 61000−4−2
and 8 A and 16 A TLP Waveforms
ESD Gun
DUT
50
W
Cable
Oscilloscope
50
W
Figure 14. Diagram of ESD Test Setup
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