Product Specification
PE4306
Product Description
The PE4306 is a high linearity, 5-bit RF Digital Step Attenuator
(DSA) covering a 31 dB attenuation range in 1dB steps, and is
pin compatible with the PE430x series. This 50-ohm RF DSA
provides both parallel (latched or direct mode) and serial
CMOS control interface, operates on a single 3-volt supply and
maintains high attenuation accuracy over frequency and
temperature. It also has a unique control interface that allows
the user to select an initial attenuation state at power-up. The
PE4306 exhibits very low insertion loss and low power
consumption. This functionality is delivered in a 4x4 mm QFN
footprint.
The PE4306 is manufactured in Peregrine’s patented Ultra
Thin Silicon (UTSi®) CMOS process, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Figure 1. Functional Schematic Diagram
Switched Attenuator Array
RF Input
RF Output
50
Ω
RF Digital Attenuator
5-bit, 31 dB, DC – 4.0 GHz
Features
•
Attenuation: 1 dB steps to 31 dB
•
Flexible parallel and serial programming
interfaces
•
Latched or direct mode
•
Unique power-up state selection
•
Positive CMOS control logic
•
High attenuation accuracy and linearity
over temperature and frequency
•
Very low power consumption
•
Single-supply operation
•
50
Ω
impedance
•
Pin compatible with PE430x series
•
Packaged in a 20 Lead 4x4 mm QFN
Figure 2. Package Type
4x4mm -20 Lead QFN
Parallel Control
Serial Control
Power-Up Control
5
3
Control Logic Interface
2
Table 1. Electrical Specifications @ +25°C, V
DD
= 3.0 V
Parameter
Operation Frequency
Insertion Loss
2
Attenuation Accuracy
1 dB Compression
3
Input IP3
1, 2
Return Loss
Switching Speed
50% control to 0.5 dB
Two-tone inputs
+18 dBm
Any Bit or Bit
Combination
DC - 2.2 GHz
DC
≤
1.0 GHz
1.0 < 2.2 GHz
1 MHz - 2.2 GHz
1 MHz - 2.2 GHz
DC - 2.2 GHz
Test Conditions
Frequency
Minimum
DC
-
-
30
-
15
-
Typical
1.5
-
34
52
20
-
Maximum
4000
2.25
±(0.3 + 3% of atten setting)
±(0.3 + 5% of atten setting)
-
-
-
1
Units
MHz
dB
dB
dB
dBm
dBm
dB
µs
Notes: 1. Device Linearity will begin to degrade below 1 Mhz
2. See Max input rating in Table 2 & Figures on Pages 2 to 4 for data across frequency.
3. Note Absolute Maximum in Table 3.
Document No. 70/0160~02C
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©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 11
PE4306
Product Specification
Typical Performance Data (25°C, V
DD
=3.0 V unless otherwise noted)
Figure 3. Insertion Loss
Figure 4. Attenuation at Major steps
0
35
31 dB
30
-1
25
-2
Normalized Error (dB)
Insertion Loss (dB)
20
16 dB
15
-3
insertion loss @ 25 C
insertion loss @ -40 C
insertion loss @ 85 C
10
8 dB
4 dB
2 dB
1 dB
0
500
1000
1500
2000
2500
3000
3500
4000
-4
5
-5
0
500
1000
1500
2000
2500
3000
3500
4000
0
Frequency (MHz)
Frequency (MHz)
Figure 5. Input Return Loss at Major
Attenuation Steps
0
Figure 6. Output Return Loss at Major
Attenuation Steps
0
-10
-10
-30
16 dB
S22 (dB)
-20
s11 (dB)
-20
-30
-40
31 dB
31 dB
-40
16 dB
-50
0
500
1000
1500
2000
2500
3000
3500
4000
-50
0
500
1000
1500
2000
2500
3000
3500
4000
Frequency (MHz)
Frequency (MHz)
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 11
Document No. 70/0160~02C
│
UltraCMOS™ RFIC Solutions
PE4306
Product Specification
Typical Performance Data (25°C, V
DD
=3.0 V unless otherwise noted)
Figure 7. Attenuation Error Vs. Frequency
Figure 8. Attenuation Error Vs. Attenuation
Setting at 10 MHz and 510 MHz
1.5
2
0
1
-2
Error (dB)
Error (dB)
0.5
31 dB
-4
0
-6
-0.5
-8
-1
10 MHz @ 25 C
510 MHz @ 25 C
10 MHz @ -40 C
510 MHz @ -40 C
10 MHz @ 85 C
510 MHz @ 85 C
0
5
10
15
20
25
30
35
-10
0
500
1000
1500
2000
2500
3000
3500
4000
-1.5
Frequency (MHz)
Attenuation State (dB)
Figure 9. Attenuation Error Vs. Attenuation
Setting 1010 MHz and 1210 MHz
1.5
Figure 10. Attenuation Error Vs. Attenuation
Setting at
1510
MHz and 2010 MHz
1.5
1
1
0.5
Error (dB)
Error (dB)
0.5
0
0
-0.5
1210 MHZ @ 25 C
1210 MHz @ -40 C
1210 MHz @ 85 C
1010 MHz @ 25 C
1010 MHz @ -40 C
1010 MHz @ 85 C
0
5
10
15
20
25
30
35
-0.5
-1
-1
1510 MHz @ 25 C
2010 MHz @ 25 C
1510 MHz @ -40 C
2010 MHz @ -40 C
1510 MHz @ 85 C
2010 MHz @ 85 C
0
5
10
15
20
25
30
35
-1.5
-1.5
Attenuation State (dB)
Attenuation State (dB)
Document No. 70/0160~02C
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©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 11
PE4306
Product Specification
Typical Performance Data (25°C, V
DD
=3.0 V unless otherwise noted)
Figure 11. Attenuation Error vs. Attenuation
Setting at
2010 MHz and 2510 MHz
1.5
Figure 12. 1 dB Compression vs. Frequency
40
1
35
0.5
Error (dB)
1 dB Compression (dBm)
0
30
0 dB
1 dB
2 dB
31 dB
-0.5
-1
2210 MHz @ 25 C
2510 MHz @ 25 C
2210 MHz @ -40 C
2510 MHz @ -40 C
2210 MHz @ 85 C
2510 MHz @ 85 C
0
5
10
15
20
25
30
35
25
-1.5
20
1000
1500
2000
Frequency (MHz)
2500
3000
Attenuation State (dB)
Figure 13. Input IP3 vs. Frequency
60
55
50
45
IP3 (dBm)
40
35
30
25
20
1000
1500
2000
Frequency (MHz)
2500
3000
0 dB
1 dB
2 dB
4 dB
8 dB
16 dB
31 dB
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 11
Document No. 70/0160~02C
│
UltraCMOS™ RFIC Solutions
PE4306
Product Specification
Figure 14. Pin Configuration (Top View)
GND
N/C
C1
C2
C4
Table 3. Absolute Maximum Ratings
Symbol
V
DD
V
I
Parameter/Conditions
Power supply voltage
Voltage on any input
Storage temperature range
Operating temperature
range
Input power (50Ω)
ESD voltage (Human Body
Model)
Min
-0.3
-0.3
-65
-40
Max
4.0
V
DD
+
0.3
150
85
24
500
Units
V
V
°C
°C
dBm
V
20
19
18
17
16
C16
RF1
Data
Clock
LE
1
2
3
4
5
10
15
C8
RF2
P/S
Vss/GND
GND
T
ST
T
OP
P
IN
V
ESD
20-lead
QFN
4x4 mm
Exposed Solder Pad
14
13
12
11
Table 4. DC Electrical Specifications
6
7
8
9
PUP1
PUP2
V
DD
V
DD
GND
Parameter
V
DD
Power Supply
Voltage
I
DD
Power Supply Current
Min
2.7
Typ
3.0
Max
3.3
100
Units
V
µA
V
Table 2. Pin Descriptions
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Paddle
Pin
Name
C16
RF1
Data
Clock
LE
V
DD
PUP1
PUP2
V
DD
GND
GND
V
ss
/GND
P/S
RF2
C8
C4
C2
GND
C1
N/C
GND
Description
Attenuation control bit, 16 dB (Note 4).
RF port (Note 1).
Serial interface data input (Note 4).
Serial interface clock input.
Latch Enable input (Note 2).
Power supply pin.
Power-up selection bit.
Power-up selection bit.
Power supply pin.
Ground connection.
Ground connection.
Negative supply voltage or GND connection
(Note 3)
Parallel/Serial mode select.
RF port (Note 1).
Attenuation control bit, 8 dB.
Attenuation control bit, 4 dB.
Attenuation control bit, 2 dB.
Ground connection.
Attenuation control bit, 1 dB.
No connect. Can be connected to any bias.
Ground for proper operation
Digital Input High
Digital Input Low
Digital Input Leakage
0.7xV
DD
0.3xV
DD
1
V
µA
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the
package must be grounded for proper device
operation.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rate specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Switching Frequency
The PE4306 has a maximum 25 kHz switching
rate.
Resistor on Pin 1 & 3
A 10 kΩ resistor on the inputs to Pin 1 & 3 (see
Figure 16) will eliminate package resonance
between the RF input pin and the two digital
inputs. Specified attenuation error versus
frequency performance is dependent upon this
condition.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 11
Notes: 1:
Both RF ports must be held at 0 V
DC
or DC blocked with an
external series capacitor.
2: Latch Enable (LE) has an internal 100 kΩ resistor to V
DD.
3: Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to V
SS
(-VDD) to bypass and
disable internal negative voltage generator.
4. Place a 10 kΩ resistor in series, as close to pin as possible
to avoid frequency resonance. See “Resistor on Pin 1 & 3”
paragraph
Document No. 70/0160~02C
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