Product Specification
PE4304
Product Description
The PE4304 is a 75-ohm high-linearity, 6-bit RF Digital Step
Attenuator (DSA) covering a 31.5 dB attenuation range in 0.5
dB steps. The PE4304 provides both a parallel (latched or
direct mode) and serial CMOS control interface, operates on a
single 3-volt supply and maintains high attenuation accuracy
over frequency and temperature. It also has a unique control
interface that allows the user to select an initial attenuation
state at power-up. The PE4304 exhibits very low insertion loss
and low power consumption. This functionality is delivered in a
4x4 mm QFN footprint.
The PE4304 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Figure 1. Functional Schematic Diagram
RF Input
75 Ω RF Digital Attenuator
6-bit, 31.5 dB, DC – 2.0 GHz
Features
75 Ω impedance
Attenuation: 0.5 dB steps to 31.5 dB
Low distortion for CATV and multi-carrier
applications
Flexible parallel and serial programming
interfaces
Unique power-up state selection
Positive CMOS control logic
High attenuation accuracy and linearity
over temperature and frequency
Very low power consumption
Single-supply operation
Packaged in a 20 lead 4x4 mm QFN
Switched Attenuator Array
Power-Up Control
Table 1. Electrical Specifications @ +25 °C, V
DD
= 3.0 V, Z
o
= 75 Ω
Parameter
Insertion Loss
2
BS
C
3
2
Serial Control
Control Logic Interface
Test Conditions
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Frequency
Minimum
DC
-
-
30
-
10
-
Parallel Control
6
O
E
DC ≤1.2 GHz
DC ≤1.2 GHz
1 MHz ≤1.2 GHz
1 MHz ≤1.2 GHz
DC ≤1.2 GHz
LE
PE
T
4x4 mm 20-Lead QFN
Figure 2. Package Type
RF Output
Typical
1.4
-
34
52
13
-
43
2000
1.8
-
-
-
1
E
14
Maximum
±(0.15 + 4% of attenuation
setting)
Units
MHz
dB
dB
dBm
dBm
dB
s
Operation Frequency
O
Attenuation Accuracy
1 dB Compression
3,4
Input IP3
1,2,4
Return Loss
Switching Speed
Notes: 1.
2.
3.
4.
Any Bit or Bit
Combination
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Two-tone inputs up to
+18 dBm
50% control to 0.5 dB
of final value
Device Linearity will begin to degrade below 1Mhz
Max input rating in Table 3 & Figures on Pages 4 to 6 for data across frequency.
Note Absolute Maximum in Table 3.
Measured in a 50 Ω system.
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
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PE4304
Product Specification
Figure 3. Pin Configuration (Top View)
GND
C0.5
C1
C2
C4
Table 3. Absolute Maximum Ratings
Symbol
V
DD
V
I
Parameter/Conditions
Power supply voltage
Voltage on any input
Storage temperature range
Input power (50Ω)
ESD voltage (Human Body
Model)
Min
-0.3
-0.3
-65
Max
4.0
V
DD
+
0.3
150
+30
500
Units
V
V
°C
dBm
V
20
19
18
17
C16
RF1
Data
Clock
LE
16
1
2
3
4
5
15
C8
RF2
P/S
Vss/GND
GND
T
ST
P
IN
V
ESD
20-lead QFN
4x4mm
Exposed Solder Pad
14
13
12
11
Table 4. Operating Ranges
Parameter
V
DD
Power Supply
Voltage
E
14
Min
2.7
10
6
7
8
9
Typ
3.0
Max
3.3
Units
V
μA
V
V
μA
dBm
°C
PUP1
PUP2
GND
V
DD
V
DD
LE
PE
T
I
DD
Power Supply
Current
Digital Input High
0.7xV
DD
Digital Input Low
Digital Input Leakage
Input Power
Temperature range
-40
100
Table 2. Pin Descriptions
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin
Name
C16
RF1
Data
Clock
LE
V
DD
PUP1
PUP2
V
DD
Description
RF port (Note 1).
0.3xV
DD
1
Attenuation control bit, 16dB (Note 4).
Serial interface data input (Note 4).
Serial interface clock input.
Latch Enable input (Note 2).
Power supply pin.
43
+24
85
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Exposed Solder Pad Connection
The exposed solder pad on the bottom of the
package must be grounded for proper device
operation.
Power-up selection bit, MSB.
Power-up selection bit, LSB.
Power supply pin.
BS
C
GND
GND
Ground connection.
Ground connection.
V
ss
/GND
P/S
Negative supply voltage or GND
connection(Note 3)
Parallel/Serial mode select.
RF port (Note 1).
RF2
C8
C4
C2
Attenuation control bit, 8 dB.
Attenuation control bit, 4 dB.
Attenuation control bit, 2 dB.
Ground connection.
GND
C1
Attenuation control bit, 1 dB.
C0.5
Attenuation control bit, 0.5 dB.
Ground for proper operation
GND
O
Paddle
EP
LA
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 11
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Note 1: Both RF ports must be DC blocked with an external series
capacitor or held at 0 V
DC
.
2: Latch Enable (LE) has an internal 100 kΩ resistor to V
DD.
3: Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to V
SS
(-V
DD
) to bypass and
disable internal negative voltage generator.
4. Place a 10 kΩ resistor in series, as close to pin as possible.
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Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rate specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Switching Frequency
The PE4304 has a maximum 25 kHz switching rate.
Resistor on Pin 1 & 3
A 10 kΩ resistor on the inputs to Pin 1 & 3 (see
Figure 5) will eliminate package resonance between
the RF input pin and the two digital inputs. Specified
attenuation error versus frequency performance is
dependent upon this condition.
Document No. 70-0066-04
│
UltraCMOS™ RFIC Solutions
PE4304
Product Specification
Evaluation Kit
The Digital Attenuator Evaluation Kit board was
designed to ease customer evaluation of the
PE4304 Digital Step Attenuator.
J9 is used in conjunction with the supplied DC cable
to supply V
DD
, GND, and –V
DD
. If use of the internal
negative voltage generator is desired, then do not
connect –V
DD
(Black banana plug). If an external –
V
DD
is desired, then apply -3V.
J1 should be connected to the parallel port of a PC
with the supplied ribbon cable. The evaluation
software is written to operate the DSA in serial
mode, so Switch 7 (P/S) should be ON with all other
switches off. Using the software, enable or disable
each attenuation setting to the desired combined
attenuation. The software automatically programs
the DSA each time an attenuation state is enabled or
disabled.
Figure 4. Evaluation Board Layout
Peregrine Specification 101/0112
BS
C
E
To power up in Parallel mode (P/S=0) with LE=0, the
control bits are automatically set to one of four
possible values. These four values are selected by
the two power-up control bits, PUP1 and PUP2, as
shown in the Parallel PUP Truth Table (Table 6).
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Note: Resistors on pins 1 and 3
are required to avoid package
resonance and meet error
specifications over frequency.
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To evaluate the Power up options, first disconnect
the parallel ribbon cable from the evaluation board.
The parallel cable must be removed to prevent the
PC parallel port from biasing the control pins to
unknown states. During power up in serial mode (P/
S=1 and LE=0) or in parallel mode with P/S=0 and
LE=1, the default power-up signal attenuation is set
to the value present on the six control bits on the six
parallel data inputs (C0.5 to C16). This allows any
one of the 64 attenuation settings to be specified as
the power-up state.
O
LE
PE
T
Figure 5. Evaluation Board Schematic
Peregrine Specification 102/0142
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
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PE4304
Product Specification
Typical Performance Data @ 25°C, V
DD
= 3.0 V (unless otherwise specified)
Figure 6. Insertion Loss
Figure 7. Attenuation at Major steps
0
35
31.5dB
30
-1
25
-2
20
-3
15
LE
PE
T
10
0.5dB
1dB
5
0
2000
0
400
800
0
-5
-10
-4
-5
0
400
800
1200
RF Frequency (MHz)
Figure 8. Input Return Loss at Major
Attenuation Steps
0
-5
-10
O
E
1200
1600
2000
Figure 9. Output Return Loss at Major
Attenuation Steps
BS
C
Input Return Loss (dB)
-15
-20
-25
-30
-35
-40
Return Loss (dB)
8dB
O
16dB
31.5dB
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0
400
800
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-15
-20
-25
-30
-35
0
400
800
1200
1600
2000
RF Frequency (MHz)
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
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Document No. 70-0066-04
│
UltraCMOS™ RFIC Solutions
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
43
1600
E
14
16dB
2dB
8dB
4dB
1200
1600
RF Frequency (MHz)
RF Frequency (MHz)
Insertion Loss (dB)
Attenuation (dB)
2000
PE4304
Product Specification
Typical Performance Data @ 25°C, V
DD
= 3.0 V (unless otherwise specified)
Figure 10. Attenuation Error Vs. Frequency
Figure 11. Attenuation Error Vs. Attenuation
Setting
0.5
1
0.5
0.25
10MHz
250MHz
Attenuation Error (dB)
Attenuation Error (dB)
8dB
-0.5
16dB
-0.25
-1
LE
PE
T
31.5dB
-0.5
-1.5
-0.75
-2
0
400
800
1200
-1
RF Frequency (MHz)
Figure 12. Attenuation Error Vs. Attenuation
Setting
0.6
0.4
BS
C
Attenuation Error (dB)
W
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10MHz, -40C
10MHz, 25C
Figure 13. Attenuation Error Vs. Attenuation
Setting
0.4
0.2
43
10
15
20
10Mhz error 85
1600
2000
0
E
14
5
10
15
20
25
30
Attenuation Setting (dB)
5
25
30
0
0
510MHz
750MHz
1010MHz
1210MHz
35
40
Error 510 Mhz
0.2
0
500MHz, -40C
O
0
E
10MHz, 85C
-0.2
500MHz, 25C
500MHz, 85C
-0.4
-0.2
EP
LA
-0.4
0
5
10
15
20
25
-0.6
30
35
40
0
35
40
Attenuation Setting (dB)
Note: Positive attenuation error indicates higher attenuation than target value
Document No. 70-0066-04
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©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
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Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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