Product Specification
PE4302
Product Description
The PE4302 is a high linearity, 6-bit RF Digital Step Attenuator
(DSA) covering a 31.5 dB attenuation range in 0.5 dB steps.
This 50-ohm RF DSA provides both parallel and serial CMOS
control interface operates on a single 3-volt supply and
maintains high attenuation accuracy over frequency and
temperature. It also has a unique control interface that allows
the user to select an initial attenuation state at power-up. The
PE4302 exhibits very low insertion loss and low power
consumption. This functionality is delivered in a 4x4 mm QFN
footprint.
The PE4302 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Figure 1. Functional Schematic Diagram
50
Ω
RF Digital Attenuator
6-bit, 31.5 dB, DC – 4.0 GHz
Features
Attenuation: 0.5 dB steps to 31.5 dB
Flexible parallel and serial programming
interfaces
Unique power-up state selection
Switched Attenuator Array
RF Input
6
Serial Control
Power-Up Control
Table 1. Electrical Specifications @ +25°C, V
DD
= 3.0 V
O
Operation Frequency
Insertion Loss
2
E
Parameter
BS
C
3
2
Control Logic Interface
Test Conditions
W
IT
H
Frequency
Minimum
DC
-
-
30
-
15
-
1.5
-
34
52
20
-
Parallel Control
O
DC - 2.2 GHz
DC
≤
1.0 GHz
1.0 < 2.2 GHz
1 MHz - 2.2 GHz
1 MHz - 2.2 GHz
DC - 2.2 GHz
LE
PE
T
50
Ω
impedance
4x4 mm 20-Lead QFN
Figure 2. Package Type
RF Output
Typical
43
4000
1.75
-
-
-
1
E
12
Positive CMOS control logic
Very low power consumption
Single-supply operation
Maximum
±(0.10 + 3% of atten setting)
±(0.15 + 5% of atten setting)
High attenuation accuracy and linearity
over temperature and frequency
Packaged in a 20 lead 4x4mm QFN
Units
MHz
dB
dB
dB
dBm
dBm
dB
s
Attenuation Accuracy
1 dB Compression
3
Input IP3
1,2
Return Loss
Switching Speed
Document No. 70-0056-04
│
www.psemi.com
R
Notes: 1. Device Linearity will begin to degrade below 1 Mhz
2. See Max input rating in Table 3 & Figures on Pages 2 to 4 for data across frequency.
3. Note Absolute Maximum in Table 3.
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 11
EP
LA
Any Bit or Bit
Combination
Two-tone inputs
+18 dBm
50% control to 0.5 dB
of final value
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE4302
Product Specification
Typical Performance Data @ 25°C, V
DD
= 3.0 V
Figure 3. Insertion Loss
Figure 4. Attenuation at Major steps
0
35
31.5dB
-1
30
25
-40C
25C
-3
85C
20
15
10
-4
LE
PE
T
8dB
5
0
4dB
-5
-6
0
500
1000
1500
2000
2500
RF Frequency (MHz)
Figure 5. Input Return Loss at Major
Attenuation Steps
0
O
E
2000
2500
3000
3500
4000
Figure 6. Output Return Loss at Major
Attenuation Steps
0
BS
C
-10
S11 (dB)
O
-30
16dB
S22 (dB)
-20
-40
31.5dB
EP
LA
-50
0
500
1000
1500
W
IT
H
-10
-20
-30
31.5dB
-40
-50
0
500
1000
1500
2000
2500
3000
3500
4000
RF Frequency (MHz)
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 11
R
Document No. 70-0056-04
│
UltraCMOS™ RFIC Solutions
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
43
3000
3500
4000
0
E
12
16dB
2dB
1dB
0.5dB
500
1000
1500
2000
2500
3000
RF Frequency (MHz)
RF Frequency (MHz)
Insertion Loss (dB)
Normalized to Insertion Loss
Attenuation (dB)
-2
3500
4000
PE4302
Product Specification
Typical Performance Data @ 25°C, V
DD
= 3.0 V
Figure 7. Attenuation Error Vs. Frequency
Figure 8. Attenuation Error Vs. Attenuation
Setting
0.5
2
0
31.5 (dB)
0
Attenuation Error (dB)
10Mhz
Attenuation Error (dB)
-4
-0.5
-6
LE
PE
T
-1
-1.5
3500
4000
0
5
10
15
0.4
0.2
Attenuation Error (dB)
10Mhz, -40C
0
500Mhz, -40C
-0.2
10Mhz, 25C
500Mhz, 25C
10Mhz, 85C
-0.8
-1
-0.4
-0.6
500Mhz, 85C
35
40
0
5
10
15
-8
-10
0
500
1000
1500
2000
2500
RF Frequency (MHz)
Figure 9. Attenuation Error Vs. Attenuation
Setting
0.6
0.4
0.2
BS
C
Attenuation Error (dB)
W
IT
H
O
E
20
25
30
Figure 10. Attenuation Error Vs. Attenuation
Setting
43
20
3000
E
12
20
25
30
Attenuation Setting (dB)
25
30
Attenuation Setting (dB)
-2
500Mhz
1000Mhz
1500Mhz
2000Mhz
2200Mhz
35
40
1000Mhz, -40C
0
1000Mhz, 25C
1500Mhz, -40C
1000Mhz, 85C
1490Mhz, 25C
1490Mhz, 85C
35
40
Note: Positive attenuation error indicates higher attenuation than target value
Document No. 70-0056-04
│
www.psemi.com
R
EP
LA
-0.6
0
5
10
15
O
-0.2
-0.4
Attenuation Setting (dB)
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 11
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE4302
Product Specification
Typical Performance Data @ 25°C, V
DD
= 3.0 V
Figure 11. Attenuation Error Vs. Frequency
Figure 12. Input IP3 Vs. Frequency
0.5
2200Mhz, -40C
60
55
50
45
40
35
30
25
20
0
Attenuation Error (dB)
2000Mhz, -40C
Input IP3 (dBm)
-0.5
2200Mhz, 25C
2000Mhz, 25C
2200Mhz, 85C
LE
PE
T
0dB
1dB
2dB
.5dB
35
40
0
500
1000
16dB
31.5dB
2500
3000
-1
2000Mhz, 85C
-1.5
0
5
10
15
20
25
30
E
12
4dB
8dB
16dB
31.5dB
Attenuation Setting (dB)
Figure 13. Input 1 dB Compression
35
1dB Compression (dBm)
30
25
O
20
15
Note: Positive attenuation error indicates higher attenuation than target value
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 11
R
EP
LA
10
BS
C
40
0dB
1dB
2dB
0.5dB
0
500
1000
1500
RF Frequency (MHz)
E
4dB
8dB
2000
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
W
IT
H
O
Document No. 70-0056-04
│
UltraCMOS™ RFIC Solutions
43
1500
2000
2500
3000
RF Frequency (MHz)
PE4302
Product Specification
Figure 14. Pin Configuration (Top View)
GND
C0.5
C1
C2
C4
Table 3. Absolute Maximum Ratings
Symbol
V
DD
V
I
Parameter/Conditions
Power supply voltage
Voltage on any DC input
Storage temperature range
Input power (50Ω)
ESD voltage (Human Body
Model)
Min
-0.3
-0.3
-65
Max
4.0
V
DD
+
0.3
150
+30
500
Units
V
V
°C
dBm
V
20
19
18
17
C16
RF1
Data
Clock
LE
16
1
2
3
4
5
10
15
C8
RF2
P/S
Vss/GND
GND
T
ST
P
IN
V
ESD
20-lead QFN
4x4mm
Exposed Solder Pad
14
13
12
11
V
DD
V
DD
PUP1
PUP2
GND
Table 2. Pin Descriptions
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
LE
PE
T
Table 4. Operating Ranges
Parameter
Min
2.7
V
DD
Power Supply
Voltage
I
DD
Power Supply
Current
Digital Input High
0.7xV
DD
Digital Input Low
Digital Input Leakage
Input Power
Temperature range
-40
Exceeding absolute maximum ratings may cause per-
manent damage. Operation should be restricted to the
limits in the Operating Ranges table. Operation be-
tween operating range maximum and absolute maxi-
mum for extended periods may reduce reliability.
E
12
Typ
3.0
6
7
8
9
Pin
Name
C16
RF1
Data
Clock
LE
V
DD
PUP1
PUP2
V
DD
Description
Max
3.3
Units
V
μA
V
Attenuation control bit, 16dB (Note 4).
RF port (Note 1).
43
100
Serial interface data input (Note 4).
Serial interface clock input.
Latch Enable input (Note 2).
Power supply pin.
0.3xV
DD
1
+24
85
V
μA
dBm
°C
Power-up selection bit, MSB.
Power-up selection bit, LSB.
Power supply pin.
BS
C
GND
GND
Ground connection.
Ground connection.
V
ss
/GND
P/S
Negative supply voltage or GND
connection(Note 3)
Parallel/Serial mode select.
RF port (Note 1).
RF2
C8
C4
C2
Attenuation control bit, 4 dB.
Attenuation control bit, 2 dB.
Ground connection.
O
GND
C1
19
20
C0.5
Paddle
GND
E
Attenuation control bit, 8 dB.
EP
LA
Attenuation control bit, 1 dB.
Attenuation control bit, 0.5 dB.
Ground for proper operation
Document No. 70-0056-04
│
www.psemi.com
R
Note 1: Both RF ports must be held at 0 V
DC
or DC blocked with an
external series capacitor.
2: Latch Enable (LE) has an internal 100 kΩ resistor to V
DD.
3: Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to V
SS
(-VDD) to bypass and
disable internal negative voltage generator.
4. Place a 10 kΩ resistor in series, as close to pin as possible
to avoid frequency resonance.
W
IT
H
O
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the package
must be grounded for proper device operation.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rate specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™ de-
vices are immune to latch-up.
Switching Frequency
The PE4302 has a maximum 25 kHz switching rate.
Resistor on Pin 1 & 3
A 10 kΩ resistor on the inputs to Pin 1 & 3 (see Figure
16) will eliminate package resonance between the RF
input pin and the two digital inputs. Specified
attenuation error versus frequency performance is
dependent upon this condition.
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 11
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
