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74ALVC132 Low Voltage Quad 2-Input NAND Gate with Schmitt Trigger Inputs and 3.6V Tolerant Inputs and
Outputs
December 2001
Revised February 2005
74ALVC132
Low Voltage Quad 2-Input NAND Gate with
Schmitt Trigger Inputs and 3.6V Tolerant Inputs
and Outputs
General Description
The ALVC132 contains four 2-input NAND gates with
Schmitt Trigger Inputs. The pin configuration and function
are the same as the ALVC00 except the inputs have hys-
teresis between the positive-going and negative-going
input thresholds. This hysteresis is useful for transforming
slowly switching input signals into sharply defined, jitter-
free output signals. This product should be used where
noise margin greater than that of conventional gates is
required.
The ALVC132 is designed for low voltage (1.65V to 3.6V)
V
CC
applications with I/O compatibility up to 3.6V.
This product is fabricated with an advanced CMOS tech-
nology to achieve high-speed operation while maintaining
low CMOS power dissipation.
Features
s
1.65V to 3.6V V
CC
supply operation
s
3.6V tolerant inputs and outputs
s
t
PD
3.8 ns max for 3.0V to 3.6V V
CC
4.6 ns max for 2.3V to 2.7V V
CC
8.2 ns max for 1.65V to 1.95V V
CC
s
Power-off high impedance inputs and outputs
s
Uses patented Quiet Series
¥
noise/EMI reduction
circuitry
s
Latchup conforms to JEDEC JED78
s
ESD performance:
Human body model
!
2000V
Machine model
!
250V
Ordering Code:
Order Number
74ALVC132M
74ALVC132MTC
Package Number
M14A
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Diagram
Connection Diagram
Pin Descriptions
Pin Name
A
n
, B
n
O
n
Description
Inputs
Outputs
Quiet Series
¥
is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS500720
www.fairchildsemi.com
74ALVC132
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Voltage (V
I
)
Output Voltage (V
O
) (Note 2)
DC Input Diode Current (I
IK
)
V
I
0V
DC Output Diode Current (I
OK
)
V
O
0V
DC Output Source/Sink Current
(I
OH
/I
OL
)
DC V
CC
or GND Current per
Supply Pin (I
CC
or GND)
Storage Temperature Range (T
STG
)
0.5V to
4.6V
0.5V to 4.6V
0.5V to V
CC
0.5V
50 mA
50 mA
r
50 mA
r
100 mA
65
q
C to
150
q
C
Recommended Operating
Conditions
(Note 3)
Power Supply
Operating
Input Voltage (V
I
)
Output Voltage (V
O
)
Free Air Operating Temperature (T
A
)
Minimum Input Edge Rate (
'
t/
'
V)
V
IN
0.8V to 2.0V, V
CC
3.0V
10 ns/V
Note 1:
The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
Note 2:
I
O
Absolute Maximum Rating must be observed.
Note 3:
Floating or unused inputs must be held HIGH or LOW.
1.65V to 3.6V
0V to V
CC
0V to V
CC
40
q
C to
85
q
C
DC Electrical Characteristics
Symbol
V
t
Positive Threshold
Parameter
Conditions
V
CC
(V)
1.65
2.3
3.0
3.6
V
t
Negative Threshold
1.65
2.3
3.0
3.6
V
H
Input Hysteresis
1.65
2.3
3.0
3.6
V
OH
HIGH Level Output Voltage
I
OH
I
OH
I
OH
I
OH
0.25
0.5
0.7
0.8
0.2
0.3
0.3
0.3
V
CC
- 0.2
1.2
2
1.7
2.2
2.4
2
0.2
0.45
0.4
0.7
0.4
0.55
V
V
0.9
1.0
1.2
1.2
V
V
Min
Max
1.3
1.6
2.0
2.2
V
Units
100
P
A
4 mA
6 mA
12 mA
1.65 - 3.6
1.65
2.3
2.3
2.7
3.0
I
OH
V
OL
LOW Level Output Voltage
I
OL
I
OL
I
OL
I
OL
I
OL
I
I
I
OZ
I
CC
Input Leakage Current
3-STATE Output Leakage
Quiescent Supply Current
Increase in I
CC
per Input
24 mA
100
P
A
4 mA
6 mA
12mA
24 mA
3.0
1.65 - 3.6
1.65
2.3
2.3
2.7
3
3.6
3.6
0
3.6
3 -3.6
0
d
V
I
d
3.6V
0
d
V
O
d
3.6V
V
I
V
IH
V
CC
or GND, I
O
V
CC
0.6V
r
5.0
r
10
40
750
P
A
P
A
P
A
P
A
'
I
CC
www.fairchildsemi.com
2
74ALVC132
AC Electrical Characteristics
T
A
Symbol
Parameter
V
CC
Min
t
PHL
, t
PLH
Propagation Delay
Bus to Bus
1.1
C
L
3.3V
r
0.3V
Max
3.8
50 pF
V
CC
Min
1.3
2.7V
Max
4.6
V
CC
Min
0.8
40
q
C to
85
q
C, R
L
500
:
C
L
2.5V
r
0.2V
Max
4.1
30 pF
V
CC
Min
1.0
1.8V
r
0.15V
Max
8.2
ns
Units
Capacitance
Symbol
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Parameter
V
I
V
I
Outputs Enabled f
0V or V
CC
0V or V
CC
10 MHz, C
L
50 pF
Conditions
T
A
V
CC
3.3
3.3
3.3
2.5
25
q
C
Typical
6
7
20
20
Units
pF
pF
pF
AC Loading and Waveforms
TABLE 1. Values for Figure 1
TEST
t
PLH
, t
PHL
SWITCH
Open
FIGURE 1. AC Test Circuit
TABLE 2. Variable Matrix
(Input Characteristics: f 1MHz; t
r
t
f
2ns; Z
0
Symbol
V
mi
V
mo
V
CC
3.3V
r
0.3V
1.5V
1.5V
2.7V
1.5V
1.5V
2.5V
r
0.2V
V
CC
/2
V
CC
/2
1.8V
r
0.15V
V
CC
/2
V
CC
/2
50
:
)
FIGURE 2. Waveform for Inverting and Non-inverting Functions
3
www.fairchildsemi.com
74ALVC132
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
www.fairchildsemi.com
4
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