BRIEF
MX28F128J3
128M [x8/x16] SINGLE 3V PAGE MODE FLASH MEMORY
FEATURES
• 2.7V to 3.6V operation voltage
• Block Structure
- 128 x 128Kbyte Erase Blocks
• Fast random / page mode access time
- 150/25 ns Read Access Time
• 128-bit Protection Register
- 64-bit Unique Device Identifier
- 64-bit User Programmable OTP Cells
• 32-Byte Write Buffer
- 6 us/byte Effective Programming Time
• Enhanced Data Protection Features Absolute Protec-
tion with VPEN = GND
- Flexible Block Locking
- Block Erase/Program Lockout during Power Transi-
tions
Software Feature
• Support Common Flash Interface (CFI)
- Flash device parameters stored on the device and
provide the host system to access.
• Automation Suspend Options
- Block Erase Suspend to Read
- Block Erase Suspend to Program
- Program Suspend to Read
Hardware Feature(Not for 48-TSOP/48-RTSOP)
• A0 pin
- Select low byte address when device is in byte mode.
Not used in word mode.
• STS pin
- Indicates the status of the internal state machine.
• VPEN pin
- For Erase /Program/ Block Lock enable.
• VCCQ Pin
- The output buffer power supply, control the device 's
output voltage.
Performance
• Low power dissipation
- typical 15mA active current for page mode read
- 80uA/(max.) standby current
- Deep power-down current: 5uA
• High Performance
- Block erase time: 2s typ.
- Byte programming time: 210us typ.
- Block programming time: 0.8s typ. (using Write to
Buffer Command)
• Program/Erase Endurance cycles: 10,000 cycles
Packaging
- 48-Lead TSOP
- 48-Lead RTSOP
- 56-Lead TSOP
- 64-ball CSP
Technology
- MX28F128J3 using Nbit (0.25u) Flash Technology
OCT/30/2002
1
MX28F128J3
GENERAL DESCRIPTION
The MXIC's MX28F128J3 series Flash use the most ad-
vance 2 bits/cell Nbit technology, double the storage ca-
pacity of memory cell. The device provide the high den-
sity Flash memory solution with reliable performance and
most cost-effective.
The device organized as by 8 bits or by 16 bits of output
bus. The device is packaged in 48-Lead TSOP, 48-Lead
RTSOP, 56-Lead TSOP, and 64-ball CSP. It is designed
to be reprogrammed and erased in system or in standard
EPROM programmers.
The device offers fast access time and allowing opera-
tion of high-speed microprocessors without wait states.
To eliminate bus contention, the device has separate chip
enable (CE0, CE1, CE2) and output enable (OE) con-
trols. The device augment EPROM functionality with in-
circuit electrical erasure and programming. The device
uses a command register to manage this functionality.
The MXIC's Nbit technology reliably stores memory con-
tents even after the specific erase and program cycles.
The MXIC cell is designed to optimize the erase and
program mechanisms by utilizing the dielectric's charac-
ter to trap or release charges from ONO layer.
The device uses a 2.7V to 3.6V VCC supply to perform
the High Reliability Erase and auto Program/Erase algo-
rithms.
The highest degree of latch-up protection is achieved
PIN CONFIGURATION
48-TSOP (12mm x 20mm) (for MX28F128J3 word mode only)
WE
A17
A16
A15
A14
A13
A12
A11
A10
A9
A20
A22
A21
A19
A18
A8
A7
A6
A5
A4
A3
A2
A1
CE0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
GND
Q15
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
VCC
A23
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
RESET(*)
MX28F128J3 (x16 only)
Normal Type
(* RESET pin : high enable)
OCT/30/2002
2
MX28F128J3
48-RTSOP (12mm x 20mm) (for MX28F128J3 word mode only)
GND
GND
Q15
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
VCC
A23
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
RESET(*)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MX28F128J3 (x16 only)
Reverse Type
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE
A17
A16
A15
A14
A13
A12
A11
A10
A9
A20
A22
A21
A19
A18
A8
A7
A6
A5
A4
A3
A2
A1
CE0
(* RESET pin : high enable)
56 TSOP (14mm x 20mm)
A22
CE1
A21
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
CE0
VPEN
RESET
A11
A10
A9
A8
GND
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
WE
OE
STS
Q15
Q7
Q14
Q6
GND
Q13
Q5
Q12
Q4
VCCQ
GND
Q11
Q3
Q10
Q2
VCC
Q9
Q1
Q8
Q0
A0
BYTE
A23
CE2
OCT/30/2002
3
MX28F128J3
64 Ball CSP (10x13x1.2mm, 1.0mm-ball pitch)
1
2
3
4
5
6
7
8
A
A1
A6
A8
VPEN
A13
VCC
A18
A22
B
A2
GND
A9
CE0
A14
DU
A19
CE1
C
A3
A7
A10
A12
A15
DU
A20
A21
D
A4
A5
A11
RESET
DU
DU
A16
A17
E
Q8
Q1
Q9
Q3
Q4
DU
Q15
STS
13 mm
F
BYTE
Q0
Q10
Q11
Q12
DU
DU
OE
G
A23
A0
Q2
VCCQ
Q5
Q6
Q14
WE
H
CE2
DU
VCC
GND
Q13
GND
Q7
NC
10mm
Notes:
1. Don't Use (DU) pins refer to pins that should not be connected.
PIN DESCRIPTION
SYMBOL
A0
A1~A23
Q0~Q15
WE
OE
RESET
RESET
PIN NAME
Byte Select Address
Address Input
Data Inputs/Outputs
Write Enable Input
Output Enable Input
Reset/Deep Power Down mode
(low enable for 56-TSOP & 64-CSP)
Reset/Deep Power Down mode
(high enable for 48-TSOP &
48-RTSOP)
SYMBOL
STS
BYTE
VPEN
VCCQ
VCC
GND
NC
DU
PIN NAME
STATUS Pin
Byte Mode Enable
ERASE/PROGRAM/BLOCK Lock
Enable
Output Buffer Power Supply
Device Power Supply
Device Ground
Pin Not Connected Internally
Don't Use
CE0, CE1, CE2 Chip Enable Input
OCT/30/2002
4
MX28F128J3
ORDERING INFORMATION
PLASTIC PACKAGE
Part NO.
MX28F128J3TBC-15
MX28F128J3RBC-15
MX28F128J3TC-15
MX28F128J3XCC-15
Access Time
(ns)
150/25
150/25
150/25
150/25
48-TSOP
48-RTSOP
56-TSOP
64-CSP
Package type
OCT/30/2002
5
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