®
BTA08, BTB08 and T8 Series
8A TRIAC
S
A2
SNUBBERLESS™, LOGIC LEVEL & STANDARD
Table 1: Main Features
Symbol
I
T(RMS)
V
DRM
/V
RRM
I
GT (Q
1
)
Value
8
600 and 800
5 to 50
Unit
A
V
mA
A1 A2
G
A2
G
A1
A2
DESCRIPTION
Available either in through-hole or surface-mount
packages, the
BTA08, BTB08
and
T8
triac series
is suitable for general purpose AC switching. They
can be used as an ON/OFF function in applica-
tions such as static relays, heating regulation, in-
duction motor starting circuits... or for phase
control operation in light dimmers, motor speed
controllers,...
The snubberless versions (BTA/BTB...W and T8
series) are specially recommended for use on
inductive loads, thanks to their high commutation
performances.
Logic level versions are designed to interface
directly with low power drivers such as
microcontrollers.
By using an internal ceramic pad, the BTA series
provides voltage insulated tab (rated at
2500V
RMS
) complying with UL standards (file ref.:
E81734).
A1
A2
G
D
2
PAK
(T8-G)
A2
IPAK
(T8-H)
A1 A2
G
DPAK
(T8-B)
A2
A1
A2
G
A1
A2
G
TO-220AB Insulated
(BTA08)
TO-220AB
(BTB08)
Table 2: Order Codes
Part Number
BTA08-xxxxxRG
BTB08-xxxxxRG
T8xx-xxxG
T8xx-xxxH
T8xx-xxxB
Marking
See page table 8 on
page 10
February 2006
REV. 6
1/11
BTA08, BTB08 and T8 Series
Table 3: Absolute Maximum Ratings
Symbol
I
T(RMS)
Parameter
RMS on-state current (full sine
wave)
IPAK/D
2
PAK/
T = 110°C
DPAK/TO-220AB
c
TO-220AB Ins.
I
TSM
I
²
t
dI/dt
I
GM
P
G(AV)
T
stg
T
j
Non repetitive surge peak on-state F = 50 Hz
current (full cycle, T
j
initial = 25°C) F = 60 Hz
I
²
t Value for fusing
Critical rate of rise of on-state cur-
rent I
G
= 2 x I
GT
, t
r
≤
100 ns
Peak gate current
Average gate power dissipation
Storage junction temperature range
Operating junction temperature range
t
p
= 10 ms
F = 120 Hz
t
p
= 20 µs
T
j
= 125°C
T
j
= 125°C
T
j
= 125°C
T
c
= 100°C
t = 20 ms
t = 16.7 ms
80
84
36
50
4
1
- 40 to + 150
- 40 to + 125
A
A
²
s
A/µs
A
W
°C
Value
8
Unit
A
Tables 4: Electrical Characteristics
(T
j
= 25°C, unless otherwise specified)
■
SNUBBERLESS and Logic Level (3 quadrants)
Symbol
I
GT
(1)
V
GT
V
GD
I
H
(2)
I
L
dV/dt (2)
Test Conditions
V
D
= 12 V R
L
= 30
Ω
Quad-
rant
I - II - III MAX.
I - II - III MAX.
MIN.
MAX.
I - III
II
MAX.
MIN.
15
25
30
40
5.4
MIN.
2.8
-
35
50
60
400
-
-
4.5
10
10
15
20
3.5
1.5
-
T8
T810 T835
10
35
TW
5
1.3
0.2
15
25
30
40
5.4
2.98
-
35
50
60
400
-
-
4.5
50
70
80
BTA08 / BTB08
SW
10
CW
35
BW
50
Unit
mA
V
V
mA
mA
V
D
= V
DRM
R
L
= 3.3 kΩ
I - II - III
T
j
= 125°C
I
T
= 100 mA
I
G
= 1.2 I
GT
V
D
= 67 %V
DRM
gate open
T
j
= 125°C
(dV/dt)c = 0.1 V/µs
T
j
= 125°C
T
j
= 125°C
T
j
= 125°C
1000 V/µs
-
-
7
A/ms
(dI/dt)c (2) (dV/dt)c = 10 V/µs
Without snubber
2/11
BTA08, BTB08 and T8 Series
■
Standard (4 quadrants)
Symbol
I
GT
(1)
V
GT
V
GD
I
H
(2)
I
L
dV/dt (2)
V
D
= V
DRM
R
L
= 3.3 kΩ T
j
= 125°C
I
T
= 500 mA
I
G
= 1.2 I
GT
V
D
= 67 %V
DRM
gate open T
j
= 125°C
T
j
= 125°C
I - III - IV
II
Test Conditions
Quadrant
I - II - III
IV
ALL
ALL
MAX.
MAX.
MIN.
MAX.
MAX.
MIN.
MIN.
25
40
80
200
5
BTA08 / BTB08
C
25
50
1.3
0.2
50
50
100
400
10
B
50
100
Unit
mA
V
V
mA
mA
V/µs
V/µs
V
D
= 12 V
R
L
= 30
Ω
(dV/dt)c (2) (dI/dt)c = 5.3 A/ms
Table 5: Static Characteristics
Symbol
V
T
(2)
V
to
(2)
R
d
(2)
I
DRM
I
RRM
I
TM
= 11 A
Test Conditions
t
p
= 380 µs
T
j
= 25°C
T
j
= 125°C
T
j
= 125°C
T
j
= 25°C
T
j
= 125°C
MAX.
MAX.
MAX.
MAX.
Value
1.55
0.85
50
5
1
Unit
V
V
mΩ
µA
mA
Threshold voltage
Dynamic resistance
V
DRM
= V
RRM
Note 1:
minimum I
GT
is guaranted at 5% of I
GT
max.
Note 2:
for both polarities of A2 referenced to A1.
Table 6: Thermal resistance
Symbol
R
th(j-c)
Junction to case (AC)
S = 1 cm
²
R
th(j-a)
Junction to ambient
S = 0.5 cm
²
Parameter
IPAK / D
2
PAK / DPAK / TO-220AB
TO-220AB Insulated
D
2
PAK
DPAK
TO-220AB / TO-220AB Insulated
IPAK
S = Copper surface under tab.
Value
1.6
2.5
45
70
60
100
Unit
°C/W
°C/W
3/11
BTA08, BTB08 and T8 Series
Figure 1: Maximum power dissipation versus
RMS on-state current (full cycle)
P(W)
10
9
8
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
Figure 2: RMS on-state current versus case
temperature (full cycle)
I
T(RMS)
(A)
10
9
8
7
6
5
4
3
2
BTA
BTB / T8
I
T(RMS)
(A)
1
0
0
25
50
T
C
(°C)
75
100
125
Figure 3: RMS on-state current versus ambient
temperature (printed circuit board FR4, copper
thickness: 35µm) (full cycle)
I
T(RMS)
(A)
3.5
3.0
2.5
D
2
PAK
(S=1CM
2
)
Figure 4: Relative variation of thermal
impedance versus pulse duration
K=[Z
th
/R
th
]
1E+0
Z
th(j-c)
DPAK/IPAK
Z
th(j-a)
1E-1
2.0
1.5
1.0
0.5
DPAK
(S=0.5CM
2
)
TO-220AB/D
2
PAK
Z
th(j-a)
1E-2
T
C
(°C)
0.0
0
25
50
75
100
125
t
p
(s)
1E-3
1E-3
1E-2
1E-1
1E+0
1E+1
1E+2
5E+2
Figure 5: On-state characteristics (maximum
values)
I
TM
(A)
100
T
j
max.
V
to
= 0.85V
R
d
= 50 m
Ω
T
j
= T
j
max.
Figure 6: Surge peak on-state current versus
number of cycles
I
TSM
(A)
90
80
70
60
50
Non repetitive
T
j
initial=25°C
Repetitive
T
C
=110°C
t=20ms
One cycle
10
T
j
= 25°C.
40
30
20
V
TM
(V)
1
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
10
0
1
10
Number of cycles
100
1000
4/11
BTA08, BTB08 and T8 Series
Figure 7: Non-repetitive surge peak on-state
current for a sinusoidal pulse with width t
p
< 10 ms
and corresponding value of I
2
t
I
TSM
(A), I t (A s)
1000
T
j
initial=25°C
2
2
Figure 8: Relative variation of gate trigger
current, holding current and latching current
versus junction temperature (typical values)
I
GT
,I
H
,I
L
[T
j
] / I
GT
,I
H
,I
L
[T
j
=25°C]
2.5
2.0
I
GT
dI/dt limitation:
50A/µs
I
TSM
1.5
1.0
I
H
& I
L
100
I
2
t
0.5
10
0.01
0.10
t
p
(ms)
1.00
10.00
T
j
(°C)
0.0
-40
-20
0
20
40
60
80
100
120
140
Figure 9: Relative variation of critical rate of
decrease of main current versus (dV/dt)c
(typical values) (Snubberless & Logic level
types)
(dI/dt)c [(dV/dt)c] / Specified (dI/dt)c
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.1
1.0
10.0
100.0
T810/SW
T835/CW/BW
TW
Figure 10: Relative variation of critical rate of
decrease of main current versus (dV/dt)c
(typical values) (Standard types)
(dI/dt)c [(dV/dt)c] / Specified (dI/dt)c
2.0
1.8
1.6
C
1.4
1.2
1.0
0.8
B
(dV/dt)c (V/µs)
0.6
0.4
0.1
1.0
(dV/dt)c (V/µs)
10.0
100.0
Figure 11: Relative variation of critical rate of
decrease of main current versus junction
temperature
Figure 12: DPAK and D
2
PAK Thermal resistance
junction to ambient versus copper surface under
tab (printed circuit board FR4, copper thickness:
35 µm)
R
th(j-a)
(°C/W)
100
90
80
70
60
50
40
30
20
D
2
PAK
DPAK
(dI/dt)c [T
j
] / (dI/dt)c [T
j
specified]
6
5
4
3
2
1
T
j
(°C)
0
0
25
50
75
100
125
10
0
0
4
8
12
16
S(cm²)
20
24
28
32
36
40
5/11
PCB设计
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
