PRELIMINARY
MX29F1610A
16M-BIT [2M x8/1M x16] CMOS
SINGLE VOLTAGE FLASH EEPROM
FEATURES
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5V
±
10% write and erase
JEDEC-standard EEPROM commands
Endurance:100,000 cycles
Fast access time: 90/100/120ns
Sector erase architecture
- 16 equal sectors of 128k bytes each
- Sector erase time: 1.3 s typical
Auto Erase and Auto Program Algorithms
- Automatically erases any one of the sectors
or the whole chip with Erase Suspend capability
- Automatically programs and verifies data at
specified addresses
Status Register feature for detection of
program or erase cycle completion
Low VCC write inhibit is equal to or less than 3.2V
Software and hardware data protection
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Page program operation
- Internal address and data latches for
128 bytes/64 words per page
- Page programming time: 0.9ms typical
- Byte programming time: 7us in average
Low power dissipation
- 30mA typical active current
- 1uA typical standby current
CMOS and TTL compatible inputs and outputs
Sector Protection
- Hardware method that can protect any combination
of sectors from write or erase operations.
Deep Power-Down Input
- 1uA ICC typical
Industry standard surface mount packaging
- 48 lead TSOP, TYPE
I
- 44 lead SOP
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GENERAL DESCRIPTION
The MX29F1610A is a 16-mega bit Flash memory
organized as either 1M wordx16 or 2M bytex8. The
MX29F1610A includes 16-128KB(131,072) blocks or 16-
64KW(65,536) blocks. MXIC's Flash memories offer the
most cost-effective and reliable read/write non-volatile
random access memory. The MX29F1610A is packaged
in 48-pin TSOP or 44-pin SOP. For 48-pin TSOP, CE2 and
RY/BY are extra pins compared with 44-pin SOP package.
This is to optimize the products (such as solid-state disk
drives or flash memory cards) control pin budget. All the
above three pins(CE2,RY/BY and PWD) plus one extra
VCC pin are not provided in 44-pin SOP. It is designed to
be reprogrammed and erased in-system or in-standard
EPROM programmers.
The standard MX29F1610A offers access times as fast as
90ns,allowing operation of high-speed microprocessors
without wait. To eliminate bus contention, the
MX29F1610A has separate chip enables(CE1 and CE2),
output enable (OE), and write enable (WE) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F1610A uses a command register to manage this
functionality. The command register allows for 100% TTL
level control inputs and fixed power supply levels during
erase and programming, while maintaining maximum
EPROM compatibility.
To allow for simple in-system reprogrammability, the
MX29F1610A does not require high input voltages for
programming. Five-volt-only commands determine the
operation of the device. Reading data out of the device
is similar to reading from an EPROM.
MXIC Flash technology reliably stores memory contents
even after 100,000 cycles. The MXIC's cell is designed
to optimize the erase and programming mechanisms. In
addition, the combination of advanced tunnel oxide
processing and low internal electric fields for erase and
programming operations produces reliable cycling. The
MX29F1610A uses a 5V
±
10% VCC supply to perform the
Auto Erase and Auto Program algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up
protection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC +1V.
P/N: PM0506
1
REV.1.7,JUN. 15, 2001
MX29F1610A
Table1.PIN DESCRIPTIONS
SYMBOL
A0 - A19
Q0 - Q7
TYPE
INPUT
INPUT/OUTPUT
NAME AND FUNCTION
ADDRESS INPUTS: for memory addresses. Addresses are internally latched
during a write cycle.
LOW-BYTE DATA BUS: Input data and commands during Command Interface
Register(CIR) write cycles. Outputs array,status and identifier data in the
appropriate read mode. Floated when the chip is de-selected or the outputs are
disabled.
HIGH-BYTE DATA BUS: Inputs data during x 16 Data-Write operations. Outputs
array, identifier data in the appropriate read mode; not used for status register
reads. Floated when the chip is de-selected or the outputs are disabled
Selects between high-byte data INPUT/OUTPUT(BYTE = HIGH) and LSB
ADDRESS(BYTE = LOW)
CHIP ENABLE INPUTS: Activate the device's control logic, Input buffers,
decoders and sense amplifiers. With either CE1 or CE2 high, the device is de-
selected and power consumption reduces to Standby level upon completion of
any current program or erase operations. Both CE1,CE2 must be low to
select the device. CE2 is not provided in 44-pin SOP package.
All timing specifications are the same for both signals. Device selection occurs
with the latter falling edge of CE1 or CE2. The first rising edge of CE1 or CE2
disables the device.
POWER-DOWN: Puts the device in deep power-down mode. PWD is active low;
PWD high gates normal operation. PWD also locks out erase or program
operation when active low providing data protection during power transitions.
OUTPUT ENABLES: Gates the device's data through the output buffers during
a read cycle OE is active low.
WRITE ENABLE: Controls writes to the Command Interface Register(CIR).
WE is active low.
READY/BUSY: Indicates the status of the internal Write State Machine(WSM).
When low it indicates that the WSM is performing a erase or program operation.
RY/BY high indicate that the WSM is ready for new commands, sector erase is
suspended or the device is in deep power-down mode. RY/BY is always active
and does not float to tristate off when the chip is deselected or data output are
disabled.
WRITE PROTECT: All sectors can be protected by writing a non-volatile protect-
bit for each sector. When WP is low, all prottect-bits status can not be changed,
i.e., the user can not execute Sector Protection and Sector Unprotect. The WP
input buffer is disabled when PWD transitions low(deep power-down mode).
BYTE ENABLE: BYTE Low places device in x8 mode. All data is then input or
output on Q0-7 and Q8-14 float. AddressQ15/A-1 selects between the high
and low byte. BYTE high places the device in x16 mode, and turns off the Q15/
A-1 input buffer. Address A0, then becomes the lowest order address.
DEVICE POWER SUPPLY(5V±10%)
GROUND
REV.1.7, JUN. 15, 2001
Q8 - Q14
INPUT/OUTPUT
.Q15/A -1
CE1/CE2
INPUT/OUTPUT
INPUT
PWD
INPUT
OE
WE
RY/BY
INPUT
INPUT
OPEN DRAIN
OUTPUT
WP
INPUT
BYTE
INPUT
VCC
GND
P/N: PM0506
4
MX29F1610A
BUS OPERATION
Flash memory reads, erases and writes in-system via the local CPU . All bus cycles to or from the flash memory conform
to standard microprocessor bus cycles.
Table 2.1 Bus Operations for Word-Wide Mode (BYTE = VIH)
Mode
Read
OutputDisable
Standby
Notes PWD CE1 CE2 OE
1,2,7
1,6,7
1,6,7
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIH
VIH
X
VIL
VIL
VIL
VIL
VIL
VIH
VIL
VIL
VIH
X
WE
VIH
VIH
X
A0
X
X
X
A1
X
X
X
A9
X
X
X
Q0-Q7
DOUT
HighZ
HighZ
Q8-Q14
DOUT
HighZ
HIghZ
Q15/A-1
DOUT
HighZ
HighZ
RY/BY
X
X
X
DeepPower-Down
1,3
4,8
4,8
1,5,6
VIL
VIH
VIH
VIH
X
VIL
VIL
VIL
X
VIL
VIL
VIH
X
VIH
VIH
VIL
X
VIL
VIH
X
X
VIL
VIL
X
X
VID
VID
X
HighZ
C2H
FAH/FBH
DIN
HighZ
00H
00H
DIN
HighZ
0B
0B
DIN
VOH
VOH
VOH
X
ManufacturerID
Device ID
MX29F1610A
Write
Table2.2 Bus Operations for Byte-Wide Mode (BYTE = VIL)
Mode
Read
OutputDisable
Standby
Notes PWD CE1 CE2 OE
1,2,7,9
1,6,7
1,6,7
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIH
VIH
X
VIL
VIL
VIL
VIL
VIL
VIH
VIL
VIL
VIH
X
WE
VIH
VIH
X
A0
X
X
X
A1
X
X
X
A9
X
X
X
Q0-Q7
DOUT
HighZ
HighZ
Q8-Q14
HighZ
HIghZ
HighZ
Q15/A-1
VIL/VIH
X
X
RY/BY
X
X
X
DeepPower-Down
1,3
4,8
4,8
1,5,6
VIL
VIH
VIH
VIH
X
VIL
VIL
VIL
X
VIL
VIL
VIH
X
VIH
VIH
VIL
X
VIL
VIH
X
X
VIL
VIL
X
X
VID
VID
X
HighZ
C2H
FAH/FBH
DIN
HIghZ
HighZ
High Z
HIghZ
X
VIL
VIL
VIL/VIH
VOH
VOH
VOH
X
ManufacturerID
Device ID
MX29F1610A
Write
NOTES :
1.X can be VIH or VIL for address or control pins except for RY/BY which is either VOL or VOH.
2.RY/BY output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode, RY/BY will be at VOH
if it is tied to VCC through a 1K ~ 100K resistor. When the RY/BY at VOH is independent of OE while a WSM operation is in progress.
3.PWD at GND ± 0.2V ensures the lowest deep power-down current.
4. A0 and A1 at VIL provide manufacturer ID codes. A0 at VIH and A1 at VIL provide device ID codes. A0 at VIL, A1 at VIH and with appropriate
sector addresses provide Sector Protect Code.(Refer to Table 4)
5. Commands for different Erase operations, Data program operations or Sector Protect operations can only be successfully completed through
proper command sequence.
6.While the WSM is running. RY/BY in Level-Mode stays at VOL until all operations are complete. RY/BY goes to VOH when the WSM is not
busy or in erase suspend mode.
7. RY/BY may be at VOL while the WSM is busy performing various operations. For example, a status register read during a write operation.
8. VID = 11.5V- 12.5V.
9. Q15/A-1 = VIL, Q0 - Q7 =D0-D7 out . Q15/A-1 = VIH, Q0 - Q7 = D8 -D15 out.
P/N: PM0506
5
REV.1.7, JUN. 15, 2001
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